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參數(shù)資料
| 型號： | 74HCT648 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Dual 4-Input Positive-NAND Gates 14-SOIC -40 to 85 |
| 中文描述： | 八路總線收發(fā)器/冊;三態(tài);反相 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 95K |
| 代理商： | 74HCT648 |
December 1990
2
Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state;
inverting
74HC/HCT648
FEATURES
Independent register for A and B buses
Multiplexed real-time and stored data
Output capability: bus driver
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT648 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT648 consist of bus transceiver circuits with
3-state inverting outputs, D-type flip-flops, and control
circuitry arranged for multiplexed transmission of data
directly from the internal registers. Data on the “A” or “B”
bus will be clocked into the registers as the appropriate
clock (CP
AB
and CP
BA
) goes to a HIGH logic level. Output
enable (OE) and direction (DIR) inputs are provided to
control the transceiver function. In the transceiver mode,
data present at the high-impedance port may be stored in
either the “A” or “B” register, or in both. The select source
inputs (S
AB
and S
BA
) can multiplex stored and real-time
(transparent mode) data. The direction (DIR) input
determines which bus will receive data when OE is active
(LOW). In the isolation mode (OE = HIGH), “A” data may
be stored in the “B” register and/or “B” data may be stored
in the “A” register.
When an output function is disabled, the input function is
still enabled and may be used to store and transmit data.
Only one of the two buses, A or B, may be driven at a time.
The “648” is functionally identical to the “646”, but has
inverting data paths.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
2.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL/
t
PLH
f
max
C
I
propagation delay A
n
, B
n
to B
n
, A
n
maximum clock frequency
input capacitance
power dissipation capacitance per
channel
C
L
= 15 pF; V
CC
= 5 V
11
75
3.5
11
88
3.5
ns
MHz
pF
C
PD
notes 1 and 2
30
31
pF
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74HC648 | Octal bus transceiver/register; 3-state; inverting |
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