參數(shù)資料
型號: 74HCT573
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: 4-Bit Synchronous Up/Down Counters (Dual Clock With Clear) 16-SOIC -40 to 85
中文描述: 八路D型透明鎖存器,三態(tài)
文件頁數(shù): 6/7頁
文件大?。?/td> 61K
代理商: 74HCT573
December 1990
6
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74HC/HCT573
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: bus driver
I
CC
category: MSI
Note to HCT types
The value of additional quiescent supply current (
I
CC
) for a unit load of 1 is given in the family specifications.
To determine
I
CC
per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
INPUT
UNIT LOAD COEFFICIENT
D
n
LE
OE
0.35
0.65
1.25
SYMBOL PARAMETER
T
amb
(
°
C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
WAVEFORMS
+25
40 to +85
40 to +125
min.
typ.
max.
min.
max.
min.
max.
t
PHL
/ t
PLH
propagation delay
D
n
to Q
n
propagation delay
LE to Q
n
3-state output enable
time
OE to Q
n
3-state output disable
time
OE to Q
n
output transition time
20
35
44
53
ns
4.5
Fig.6
t
PHL
/ t
PLH
18
35
44
53
ns
4.5
Fig.7
t
PZH
/ t
PZL
17
30
38
45
ns
4.5
Fig.8
t
PHZ
/ t
PLZ
18
30
38
45
ns
4.5
Fig.8
t
THL
/ t
TLH
5
12
15
18
ns
4.5
Fig.6
t
W
enable pulse width
HIGH
set-up time
D
n
to LE
hold time
D
n
to LE
16
5
20
24
ns
4.5
Fig.7
t
su
13
7
16
20
ns
4.5
Fig.9
t
h
9
4
11
14
ns
4.5
Fig.9
相關PDF資料
PDF描述
74HC573 Octal D-type transparent latch; 3-state
74HCT573PW 4-Bit Synchronous Up/Down Counters (Dual Clock With Clear) 16-PDIP -40 to 85
74HC573 Octal 3-State Noninverting Transparent Latch(High-Performance Silicon-Gate CMOS)
74HCT574 4-Bit Synchronous Up/Down Counters (Dual Clock With Clear) 16-SO -40 to 85
74HC574 Octal D-type flip-flop; positive edge-trigger; 3-state
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