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參數(shù)資料
| 型號(hào)： | 74HCT564 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通用總線功能 |
| 英文描述： | 4-Bit Synchronous Up/Down Counters (Dual Clock With Clear) 16-SOIC -40 to 85 |
| 中文描述： | 八路D型觸發(fā)器;陽性沿觸發(fā)，3態(tài);反相 |
| 文件頁數(shù)： | 6/7頁 |
| 文件大小： | 58K |
| 代理商： | 74HCT564 |
December 1990
6
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive-edge trigger;
3-state; inverting
74HC/HCT564
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: bus driver
I
CC
category: MSI
Note to HCT types
The value of additional quiescent supply current (
I
CC
) for a unit load of 1 is given in the family specifications.
To determine
I
CC
per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
INPUT
UNIT LOAD COEFFICIENT
OE
D
0
to D
7
CP
0.80
0.25
1.00
SYMBOL PARAMETER
T
amb
(
°
C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
WAVEFORMS
+25
40 to +85
40 to +125
min.
typ.
max.
min.
max.
min.
max.
t
PHL
/ t
PLH
propagation delay
CP to Q
n
3-state output enable
time OE to Q
n
3-state output disable
time OE to Q
n
output transition time
19
35
44
53
ns
4.5
Fig.6
t
PZH
/ t
PZL
19
35
44
53
ns
4.5
Fig.8
t
PHZ
/ t
PLZ
19
30
38
45
ns
4.5
Fig.8
t
THL
/ t
TLH
5
12
15
18
ns
4.5
Fig.6
t
W
clock pulse width
HIGH or LOW
set-up time
D
n
to CP
hold time
D
n
to CP
maximum clock pulse
frequency
18
8
23
27
ns
4.5
Fig.6
t
su
12
3
15
18
ns
4.5
Fig.7
t
h
3
2
3
3
ns
4.5
Fig.7
f
max
27
56
22
18
MHz
4.5
Fig.6
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|---|---|
| 74HC564 | Octal D-type flip-flop; positive-edge trigger; 3-state; inverting |
| 74HCT564D | Octal D-type flip-flop; positive-edge trigger; 3-state; inverting |
| 74HCT564N | 4-Bit Synchronous Up/Down Counters (Dual Clock With Clear) 16-SOIC -40 to 85 |
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