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參數(shù)資料
| 型號： | 74HCT4520DB,112 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 7/7頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DUAL 4BIT SYNC BINARY 16-SSOP |
| 產(chǎn)品培訓(xùn)模塊： | Logic Packages |
| 標準包裝： | 78 |
| 系列： | 74HCT |
| 邏輯類型： | 二進制計數(shù)器 |
| 方向： | 上 |
| 元件數(shù)： | 2 |
| 每個元件的位元數(shù)： | 4 |
| 復(fù)位： | 異步 |
| 計時： | 同步 |
| 計數(shù)速率： | 58MHz |
| 觸發(fā)器類型： | 正，負 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SSOP |
| 包裝： | 管件 |
| 其它名稱： | 568-2880-5 935190110112 |
74LVCH322244A
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 16 December 2011
7 of 14
NXP Semiconductors
74LVCH322244A
32-bit buffer/line driver; 30
resistors; 5 V tolerance; 3-state
[1]
Typical values are measured at Tamb =25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.
[2]
tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[3]
Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4]
CPD is used to determine the dynamic power dissipation (PD in W).
PD =CPD VCC2 fi N+ (CL VCC2 fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
(C
L VCC
2
f
o) = sum of the outputs
11. AC waveforms
tsk(o)
output skew
time
VCC = 3.0 V to 3.6 V
-
1.0
-
1.5
ns
CPD
power
dissipation
capacitance
per flip-flop; VI =GND to VCC
outputs enabled
VCC = 1.65 V to 1.95 V
-
4.8
-
pF
VCC = 2.3 V to 2.7 V
-
8.3
-
pF
VCC = 3.0 V to 3.6 V
-
11.4
-
pF
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 6.
Symbol Parameter
Conditions
Tamb = 40 C to +85 C 40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
VM = 1.5 V at VCC 2.7 V or
VM = 0.5 VCC at VCC < 2.7 V.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 4.
Input (nAn) to output (nYn) propagation delay times
mna474
nAn input
nYn output
tPHL
tPLH
GND
VI
VM
VOH
VOL
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