參數(shù)資料
型號(hào)： 74HCT4520
廠商： Texas Instruments, Inc.
元件分類(lèi)： 通用總線功能
英文描述： 4-Bit Synchronous Up/Down Binary Counters 16-SOIC -40 to 85
中文描述： 高速CMOS邏輯雙同步計(jì)數(shù)器
文件頁(yè)數(shù)： 2/7頁(yè)
文件大小： 55K
代理商： 74HCT4520
December 1990
2
Philips Semiconductors
Product specification
Dual 4-bit synchronous binary counter
74HC/HCT4520
FEATURES
Output capability: standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4520 are high-speed Si-gate CMOS
devices and are pin compatible with the “4520” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4520 are dual 4-bit internally synchronous
binary counters with an active HIGH clock input (nCP
0
)
and an active LOW clock input (nCP
1
), buffered outputs
from all four bit positions (nQ
0
to nQ
3
) and an active HIGH
overriding asynchronous master reset input (nMR).
The counter advances on either the LOW-to-HIGH
transition of nCP
0
if nCP
1
is HIGH or the HIGH-to-LOW
transition of nCP
1
if nCP
0
is LOW. Either nCP
0
or nCP
1
may be used as the clock input to the counter and the other
clock input may be used as a clock enable input. A HIGH
on nMR resets the counter (nQ
0
to nQ
3
= LOW)
independent of nCP
0
and nCP
1
.
APPLICATIONS
Multistage synchronous counting
Multistage asynchronous counting
Frequency dividers
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
2.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
t
PHL
f
max
C
I
C
PD
propagation delay nCP
0
, nCP
1
to nQ
n
propagation delay nMR to nQ
n
maximum clock frequency
input capacitance
power dissipation capacitance per counter
C
L
= 15 pF; V
CC
= 5 V 24
24
13
64
3.5
24
ns
ns
MHz
pF
pF
13
68
3.5
29
notes 1 and 2
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