參數(shù)資料
型號: 74HCT4516
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: 4-Bit Synchronous Up/Down Binary Counters 16-SOIC -40 to 85
中文描述: 二進制向上/向下計數(shù)器
文件頁數(shù): 13/14頁
文件大?。?/td> 100K
代理商: 74HCT4516
December 1990
13
Philips Semiconductors
Product specification
Binary up/down counter
74HC/HCT4516
APPLICATION INFORMATION
Fig.12 Cascading counter packages (parallel clocking).
Terminal count (TC) lines at the 2nd, 3rd, etc. Stages may have a negative-going glitch pulse resulting from differential
delays of different 4516s. These negative-going glitches do not affect proper 4516 operation. However, if the terminal
count signals are used to trigger other edge-sensitive logic devices, such as flip-flops or counters, the terminal count
signals should be gated with the clock signal using a 2-input OR gate such as HC/HCT32.
Fig.13 Cascading counter packages (ripple clocking).
Ripple clocking mode: the UP/DN control can be changed at any count. The only restriction on changing the
UP/DN control is that the clock input to the first counting stage must be “HIGH”. For cascading counters operating in a
fixed up-count or down-count mode, the OR gates are not required between stages and TC is connected directly to the
CP input of the next stage with CE grounded.
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