參數(shù)資料
型號: 74HCT4353
廠商: NXP Semiconductors N.V.
英文描述: Triple 2-channel analog multiplexer/demultiplexer with latch(帶鎖存的三端2通道模擬多路復(fù)用器/多路分解器)
中文描述: 三2通道模擬多路復(fù)用器/分離器的鎖存器(帶鎖存的三端2通道模擬多路復(fù)用器/多路分解器)
文件頁數(shù): 2/16頁
文件大?。?/td> 136K
代理商: 74HCT4353
December 1990
2
Philips Semiconductors
Product specification
Triple 2-channel analog
multiplexer/demultiplexer with latch
74HC/HCT4353
FEATURES
Wide analog input voltage range:
±
5 V
Low “ON” resistance:
80
(typ.) at V
CC
V
EE
= 4.5 V
70
(typ.) at V
CC
V
EE
= 6.0 V
60
(typ.) at V
CC
V
EE
= 9.0 V
Logic level translation:
to enable 5 V logic to communicate with
±
5 V analog
signals
Typical “break before make” built in
Address latches provided
Output capability: non-standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4353 are high-speed Si-gate CMOS
devices. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT4353 are triple 2-channel analog
multiplexers/demultiplexers with two common enable
inputs (E
1
and E
2
) and a latch enable input (LE). Each
multiplexer has two independent inputs/outputs (nY
0
and
nY
1
), a common input/output (nZ) and select inputs (S
1
to
S
3
).
Each multiplexer/demultiplexer contains two bidirectional
analog switches, each with one side connected to an
independent input/output (nY
0
and nY
1
) and the other side
connected to a common input/output (nZ).
With E
1
LOW and E
2
HIGH, one of the two switches is
selected (low impedance ON-state) by S
1
to S
3
.
The data at the select inputs may be latched by using the
active LOW latch enable input (LE). When LE is HIGH, the
latch is transparent. When either of the two enable inputs,
E
1
(active LOW) and E
2
(active HIGH), is inactive, all
analog switches are turned off.
V
CC
and GND are the supply voltage pins for the digital
control inputs (S
1
to S
3
, LE, E
1
and E
2
). The V
CC
to GND
ranges are 2.0 to 10.0 V for HC and 4.5 to 5.5 V for HCT.
The analog inputs/outputs (nY
0
and nY
1
, and nZ) can
swing between V
CC
as a positive limit and V
EE
as a
negative limit. V
CC
V
EE
may not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, V
EE
is
connected to GND (typically ground).
QUICK REFERENCE DATA
V
EE
= GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PZH
/ t
PZL
t
PHZ
/ t
PLZ
C
I
C
PD
C
S
turn “ON” time E
1
, E
2
or S
n
to V
os
turn “OFF” time E
1
, E
2
or S
n
to V
os
input capacitance
power dissipation capacitance per switch
max. switch capacitance
independent (Y)
common (Z)
C
L
= 50 pF; R
L
= 1 k
;
V
CC
= 5 V
29
20
3.5
23
21
22
3.5
23
ns
ns
pF
pF
notes 1 and 2
5
8
5
8
pF
pF
Notes
1.
C
PD
is used to determine the dynamic power
dissipation (P
D
in
μ
W):
P
D
=
C
PD
×
V
CC2
×
f
i
+
{(C
L
+ C
S
)
×
V
CC2
×
f
o
} where:
f
i
= input frequency in MHz
C
L
= output load capacitance in pF
f
o
= output frequency in MHz
C
S
= max. switch capacitance in pF
{(C
L
×
C
S
)
×
V
CC2
×
f
o
} = sum of outputs
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
2.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package
Information”
.
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