參數(shù)資料
型號: 74HCT4352
廠商: NXP Semiconductors N.V.
英文描述: Quadruple D-Type Flip-Flops With Clear 16-TSSOP -40 to 85
中文描述: 雙4通道模擬多路復(fù)用器/解復(fù)用器的鎖存
文件頁數(shù): 2/16頁
文件大?。?/td> 125K
代理商: 74HCT4352
December 1990
2
Philips Semiconductors
Product specification
Dual 4-channel analog
multiplexer/demultiplexer with latch
74HC/HCT4352
FEATURES
Wide analog input voltage range:
±
5 V.
Low “ON” resistance:
80
(typ.) at V
CC
V
EE
= 4.5 V
70
(typ.) at V
CC
V
EE
= 6.0 V
60
(typ.) at V
CC
V
EE
= 9.0 V
Logic level translation:
to enable 5 V logic to communicate with
±
5 V analog
signals
Typical “break before make” built in
Address latches provided
Output capability: non-standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4352 are high-speed Si-gate CMOS
devices. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT4352 are dual 4-channel analog
multiplexers/demultiplexers with common select logic.
Each multiplexer has four independent inputs/outputs
(nY
0
to nY
3
) and a common input/output (nZ).
The common channel select logics include two select
inputs (S
0
and S
1
), an active LOW enable input (E
1
), an
active HIGH enable input (E
2
) and a latch enable input
(LE).
With E
1
LOW and E
2
HIGH, one of the four switches is
selected (low impedance ON-state) by S
0
and S
1
. The data
at the select inputs may be latched by using the active
LOW latch enable input (LE). When LE is HIGH, the latch
is transparent. When either of the two enable inputs, E
1
(active LOW) and E
2
(active HIGH), is inactive, all analog
switches are turned off.
V
CC
and GND are the supply voltage pins for the digital
control inputs (S
0
, S
1
, LE, E
1
and E
2
). The V
CC
to GND
ranges are 2.0 to 10.0 V for HC and 4.5 to 5.5 V for HCT.
The analog inputs/outputs (nY
0
to nY
3
, and nZ) can swing
between V
CC
as a positive limit and V
EE
as a negative limit.
V
CC
V
EE
may not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, V
EE
is
connected to GND (typically ground).
QUICK REFERENCE DATA
V
EE
= GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑ {
(C
L
+
C
S
) ×
V
CC2
×
f
o
} where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
{ (C
L
+
C
S
) ×
V
CC2
×
f
o
} = sum of outputs
C
L
= output load capacitance in pF
C
S
= max. switch capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
2.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PZH
/ t
PZL
t
PHZ
/ t
PLZ
C
I
C
PD
C
S
turn “ON” time E
1
, E
2
or S
n
to V
os
turn “OFF” time E
1
, E
2
or S
n
to V
os
input capacitance
power dissipation capacitance per switch
max. switch capacitance
independent (Y)
common (Z)
C
L
= 15 pF; R
L
= 1 k
;
V
CC
= 5 V
31
20
3.5
55
33
20
3.5
55
ns
ns
pF
pF
notes 1 and 2
5
12
5
12
pF
pF
相關(guān)PDF資料
PDF描述
74HC4352 Dual 4-channel analog multiplexer/demultiplexer with latch
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