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參數(shù)資料
| 型號： | 74HCT4059N,112 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 5/20頁 |
| 文件大小： | 0K |
| 描述： | IC COUNTER PROGRAM DIV X N 24DIP |
| 產(chǎn)品培訓(xùn)模塊： | Logic Packages |
| 標(biāo)準(zhǔn)包裝： | 15 |
| 系列： | 74HCT |
| 邏輯類型： | 除以 N |
| 方向： | 下 |
| 元件數(shù)： | 1 |
| 每個元件的位元數(shù)： | 16 |
| 復(fù)位： | 異步 |
| 計時： | 同步 |
| 計數(shù)速率： | 36MHz |
| 觸發(fā)器類型： | 正邊沿 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 24-DIP（0.600"，15.24mm） |
| 供應(yīng)商設(shè)備封裝： | 24-DIP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 837 (CN2011-ZH PDF) |
| 其它名稱： | 568-1550-5 74HCT4059N 933757420112 |
1998 Jul 08
13
Philips Semiconductors
Product specication
Programmable divide-by-n counter
74HC/HCT4059
The arrangement shown in Fig.12 is easy to follow; once
during every cycle the programmed digits are jammed in
(15 616 in this example) and then a round number of
11 000 is jammed in, nine times in succession, by forcing
the JAM inputs via AND/OR gates.
Numbers larger than the extended counter range can also
be produced by cascading the PC74HC/HCT4059 with
some other counting devices. Figure 13 shows such an
arrangement where only one fixed divide-by number is
desired. The dual flip-flop wired to produce a divide-by-3
count can be replaced by other counters such as the “190”,
“191”, “192”, “193”, “4017”, “4510” and “4516”.
In Fig.13 the divide-by-n sub-system is preset once to a
number which represents the least significant digits of the
divide-by number (15 690 in the example shown in Fig.13).
The sub-system is then preset twice to a round number
(8 000 in the example shown in Fig.13) and multiplied by
the number of the divide-by mode (2 in the example shown
in Fig.13).
To verify:
15 690
+ 2 × 8 000 × 2 = 47 690.
It is important that the second counting device has an
output that is HIGH or LOW during only one of its counting
states.
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