參數(shù)資料
型號： 74HCT4017PW
廠商： NXP SEMICONDUCTORS
元件分類： 通用總線功能
英文描述： Johnson decade counter with 10 decoded outputs
中文描述： HCT SERIES, SYN POSITIVE EDGE TRIGGERED 10-BIT UP RING COUNTER, PDSO16
文件頁數(shù)： 12/12頁
文件大小： 102K
代理商： 74HCT4017PW
December 1990
12
Philips Semiconductors
Product specification
Johnson decade counter with 10 decoded outputs
74HC/HCT4017
APPLICATION INFORMATION
Some applications for the “4017” are:
Decade counter with decimal decoding
1 out of n decoding counter (when cascaded)
Sequential controller
Timer
Figure 10 shows a technique for extending the number of decoded output states for the “4017”. Decoded outputs are
sequential within each stage and from stage to stage, with no dead time (except propagation delay).
Figure 11 shows an example of a divide-by 2 through divide-by 10 circuit using one “4017”. Since “4017” has an
asynchronous reset, the output pulse widths are narrow (minimum expected pulse width is 6 ns). The output pulse widths
can be enlarged by inserting a RC network at the MR input.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
Fig.10 Counter expansion
It is essential not to enable the counter on CP
when CP
is HIGH, or on CP
when CP
1
is LOW,
as this would cause an extra count.
Fig.11 Divide-by 2 through divide-by 10.
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