參數(shù)資料
型號: 74HCT4017
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: Johnson decade counter with 10 decoded outputs(帶10解碼輸出的十進制約翰遜計數(shù)器)
中文描述: 約翰遜以10解碼輸出十年計數(shù)器(帶10解碼輸出的十進制約翰遜計數(shù)器)
文件頁數(shù): 2/12頁
文件大?。?/td> 86K
代理商: 74HCT4017
December 1990
2
Philips Semiconductors
Product specification
Johnson decade counter with 10 decoded outputs
74HC/HCT4017
FEATURES
Output capability: standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4017 are high-speed Si-gate CMOS
devices and are pin compatible with the “4017” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4017 are 5-stage Johnson decade
counters with 10 decoded active HIGH outputs (Q
0
to Q
9
),
an active LOW output from the most significant flip-flop
(Q
5-9
), active HIGH and active LOW clock inputs (CP
0
and
CP
1
) and an overriding asynchronous master reset input
(MR).
The counter is advanced by either a LOW-to-HIGH
transition at CP
0
while CP
1
is LOW or a HIGH-to-LOW
transition at CP
1
while CP
0
is HIGH (see also function
table).
When cascading counters, the Q
5-9
output, which is LOW
while the counter is in states 5, 6, 7, 8 and 9, can be used
to drive the CP
0
input of the next counter.
A HIGH on MR resets the counter to zero
(Q
0
= Q
5-9
= HIGH; Q
1
to Q
9
= LOW) independent of the
clock inputs (CP
0
and CP
1
).
Automatic code correction of the counter is provided by an
internal circuit: following any illegal code the counter
returns to a proper counting mode within 11 clock pulses.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
2.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
f
max
C
I
C
PD
propagation delay CP
0
, CP
1
to Q
n
maximum clock frequency
input capacitance
power dissipation capacitance per package
C
L
= 15 pF; V
CC
= 5 V 20
21
67
3.5
36
ns
MHz
pF
pF
77
3.5
35
notes 1 and 2
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