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參數(shù)資料
| 型號： | 74HCT354 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 8-Bit Parallel-Load Shift Registers 16-SOIC -40 to 85 |
| 中文描述： | 8輸入多路復(fù)用器/注冊透明鎖存器，三態(tài) |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 82K |
| 代理商： | 74HCT354 |
December 1990
2
Philips Semiconductors
Product specification
8-input multiplexer/register with
transparent latches; 3-state
74HC/HCT354
FEATURES
Transparent data latches
Transparent address latch
Easily expanding
Complementary outputs
Output capability: bus driver
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT354 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT354 data selectors/multiplexers contain full
on-chip binary decoding, to select one-of-eight data
sources. The data select address is stored in transparent
latches that are enabled by a LOW on the latch enable
input (LE).
The transparent 8-bit data latches are enabled when the
active LOW data enable input (E) is LOW. When the output
enable input OE
1
= HIGH, OE
2
= HIGH or OE
3
= LOW,
the outputs go to the high impedance OFF-state.
Operation of these output enable inputs does not affect the
state of the latches.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
2.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL/
t
PLH
propagation delay
D
n
, E to Y, Y
S
n
, LE to Y, Y
input capacitance
power dissipation capacitance per latch
C
L
= 15 pF; V
CC
= 5 V
20
24
3.5
68
22
27
3.5
71
ns
ns
pF
pF
C
I
C
PD
notes 1 and 2
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| 74HC354 | 8-input multiplexer/register with transparent latches; 3-state |
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