參數(shù)資料
型號: 74HCT258
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: 4-Bit Synchronous Binary Counters 16-TSSOP -40 to 85
中文描述: 四2輸入多路復(fù)用器,三態(tài);反相
文件頁數(shù): 2/16頁
文件大?。?/td> 83K
代理商: 74HCT258
1999 Sep 02
2
Philips Semiconductors
Product specification
Quad 2-input multiplexer; 3-state; inverting
74HC/HCT258
FEATURES
Inverting data path
3-state outputs interface directly with system bus
Output capability: bus driver
I
CC
category: MSI.
GENERAL DESCRIPTION
The74HC/HCT258arehigh-speedSi-gateCMOSdevices
and are pin compatible with Low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The74HC/HCT258havefouridentical2-inputmultiplexers
with 3-state outputs, which select 4 bits of data from two
sources and are controlled by a common data select
input (S).
The data inputs from source 0 (1I
0
to 4I
0
) are selected
when input S is LOW and the data inputs from source 1
(1I
1
to 4I
1
) are selected when S is HIGH.
Data appears at the outputs (1Y to 4Y) in inverted form
from the select inputs.
The‘258’isthelogicimplementationofa4-pole,2-position
switch, where the position of the switch is determined by
the logic levels applied to S. The outputs are forced to a
high impedance OFF-state when OE is HIGH.
The logic equations for the outputs are:
The ‘258’ is identical to the ‘257’ but has inverting outputs.
1Y
OE
1I
1
S
×
1I
0
S
×
+
(
)
×
=
2Y
OE
2I
1
S
×
2I
0
S
×
+
(
)
×
=
3Y
OE
3I
1
S
×
3I
0
S
×
+
(
)
×
=
4Y
OE
4I
1
S
×
4I
0
S
×
+
(
)
×
=
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns.
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
(C
L
×
V
CC2
×
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
For HC the condition is V
I
= GND to V
CC
;
For HCT the condition is V
I
= GND to V
CC
1.5 V.
2.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/t
PLH
propagation delay
nI
0
, nI
1
to nY
S to nY
input capacitance
power dissipation capacitance per multiplexer
C
L
= 15 pF;
V
CC
= 5 V
9
14
3.5
55
13
16
3.5
38
ns
ns
pF
pF
C
I
C
PD
notes 1 and 2
相關(guān)PDF資料
PDF描述
74HC258 Quad 2-input multiplexer; 3-state; inverting
74HCT258D Quad 2-input multiplexer; 3-state; inverting
74HCT258N Quad 2-input multiplexer; 3-state; inverting
74HCT259 8-bit addressable latch
74HC259 8-bit addressable latch
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