參數(shù)資料
型號: 74HCT193
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: Presettable synchronous 4-bit binary up/down counter
中文描述: 可預(yù)置同步4位二進制加/減計數(shù)器
文件頁數(shù): 12/13頁
文件大?。?/td> 95K
代理商: 74HCT193
December 1990
12
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
up/down counter
74HC/HCT193
Fig.10 Waveforms showing the master reset input (MR) pulse width, MR to Q
n
propagation delays, MR to CP
U
,
CP
D
removal time and output transition times.
(1) HC : V
M
= 50%; V
I
= GND to V
.
HCT: V
M
= 1.3V; V
I
= GND to 3 V.
Fig.11 Waveforms showing the data input (D
n
) to parallel load input (PL) set-up and hold times.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : V
M
= 50%; V
I
= GND to V
.
HCT: V
M
= 1.3V; V
I
= GND to 3 V.
Fig.12 Waveforms showing the data input (D
n
), parallel load input (PL) and the master reset input (MR) to the
terminal count outputs (TC
U
, TC
D
) propagation delays.
(1) HC : V
M
= 50%; V
I
= GND to V
.
HCT: V
M
= 1.3V; V
I
= GND to 3 V.
Fig.13 Waveforms showing the CP
U
to CP
D
or CP
D
to CP
U
hold times.
(1) HC : V
M
= 50%; V
I
= GND to V
.
HCT: V
M
= 1.3V; V
I
= GND to 3 V.
相關(guān)PDF資料
PDF描述
74HC193 Presettable synchronous 4-bit binary up/down counter
74HCT194 4-bit bidirectional universal shift register
74HC194 4-bit bidirectional universal shift register
74HCT195 4-bit parallel access shift register
74HC195 4-bit parallel access shift register
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