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參數(shù)資料
| 型號： | 74HCT166PW |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | Quadruple 2-Line To 1-Line Data Selectors/Multiplexers 16-SO -40 to 85 |
| 中文描述： | HCT SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16 |
| 封裝： | PLASTIC, TSSOP1-16 |
| 文件頁數(shù)： | 2/10頁 |
| 文件大小： | 93K |
| 代理商： | 74HCT166PW |
December 1990
2
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74HC/HCT166
FEATURES
Synchronous parallel-to-serial applications
Synchronous serial data input for easy expansion
Clock enable for “do nothing” mode
Asynchronous master reset
For asynchronous parallel data load see “165”
Output capability: standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT166 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT166 are 8-bit shift registers which have a
fully synchronous serial or parallel data entry selected by
an active LOW parallel enable (PE) input. When PE is
LOW one set-up time prior to the LOW-to-HIGH clock
transition, parallel data is entered into the register. When
PE is HIGH, data is entered into the internal bit position Q
0
from serial data input (D
s
), and the remaining bits are
shifted one place to the right (Q
0
→
Q
1
→
Q
2
, etc.) with
each positive-going clock transition.
This feature allows parallel-to-serial converter expansion
by tying the Q
7
output to the D
s
input of the succeeding
stage.
The clock input is a gated-OR structure which allows one
input to be used as an active LOW clock enable (CE) input.
The pin assignment for the CP and CE inputs is arbitrary
and can be reversed for layout convenience. The
LOW-to-HIGH transition of inputCE should only take place
while CP is HIGH for predictable operation. A LOW on the
master reset (MR) input overrides all other inputs and
clears the register asynchronously, forcing all bit positions
to a LOW state.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
2.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
propagation delay
CP to Q
7
MR to Q
7
maximum clock frequency
input capacitance
power dissipation capacitance per package
C
L
= 15 pF; V
CC
= 5 V
15
14
63
3.5
41
20
19
50
3.5
41
ns
ns
MHz
pF
pF
f
max
C
I
C
PD
notes 1 and 2
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