參數(shù)資料
型號: 74HCT109
廠商: NXP Semiconductors N.V.
英文描述: 8-Line To 3-Line Priority Encoders 16-SOIC -40 to 85
中文描述: 雙JK觸發(fā)器設(shè)置和復(fù)位觸發(fā)器,積極邊緣觸發(fā)
文件頁數(shù): 7/9頁
文件大?。?/td> 65K
代理商: 74HCT109
1997 Nov 25
7
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
74HC/HCT109
AC WAVEFORMS
Fig.6
Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nJ,
nK to nCP set-up, the nCP to nJ, nK hold times, the output transition times and the maximum clock pulse
frequency.
The shaded areas indicate when the
input is permitted to change for
predictable output performance.
handbook, full pagewidth
MBK216
VM
(1)
nCP INPUT
nSD INPUT
nRD INPUT
nQ OUTPUT
nQ OUTPUT
VM
(1)
VM
(1)
VM
(1)
VM
(1)
tW
trem
trem
tW
tPHL
tPLH
tPLH
tPHL
Fig.7
Waveforms showing the set (nS
D
) and reset (nR
D
) input to output (nQ, nQ) propagation delays, the set
and reset pulse widths and the nR
D
, nS
D
to nCP removal time.
(1) HC: V
M
= 50%; V
I
= GND to V
.
HCT: V
M
= 1.3 V; V
I
= GND to 3 V.
相關(guān)PDF資料
PDF描述
74HC109PW Dual JK flip-flop with set and reset; positive-edge trigger
74HC112 Dual JK flip-flop with set and reset; negative-edge trigger
74HCT112 8-Line To 3-Line Priority Encoders 16-SO -40 to 85
74HC11 Triple 3-input AND gate
74HCT11 8-Line To 3-Line Priority Encoders 16-SO -40 to 85
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