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參數資料
| 型號： | 74HC9323A |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通用總線功能 |
| 英文描述： | Programmable ripple counter with oscillator 3-State |
| 中文描述： | 紋波計數器可編程振蕩器三態(tài) |
| 文件頁數： | 2/6頁 |
| 文件大?。?/td> | 44K |
| 代理商： | 74HC9323A |
Philips Semiconductors
Objective specification
74HC/HCT9323A
Programmable ripple counter with oscillator
(3-State)
2
1995 Oct 27
FEATURES
8-pin space saving package
Programmable 3-stage ripple counter
Suitable for over-tone crystal application up to 85MHz
(V
CC
= 5V
10%)
3-State output buffer
Two internal capacitors
Recommended operating range for use with third overtone
crystals 3V to 6V
Oscillator stop function (MR)
Output capability:
bus driver
(15 LSTTL)
I
CC
category: MSI
APPLICATIONS
Control counters
Timers
Frequency dividers
Time-delay circuits
CIO (Compact Integrated Oscillator)
Third-overtone crystal operation
DESCRIPTION
The 74HC/HCT9323A are high-speed Si-gate CMOS devices. They
are specified in compliance with JEDEC standard no. 7A.
The HC/HCT 9323A are oscillators designed for quartz crystal
combined with a programmable 3-State counter, a 3-State output
buffer and an overriding asynchronous master reset (MR). With the
two select inputs S1 and S2 the counter can be switched in the
divide-1, 2, 4 or 8 mode. If left floating the clock is divided by 8. The
oscillator is designed to operate either in the fundamental or third
overtone mode depending on the crystal and external components
applied. On-chip capacitors minimize external component count for
third overtone crystal applications.
The oscillator may be replaced by an external clock signal at input
X1. In this event the other oscillator pin (X2) must be floating. The
counter advances on the negative-going transition of X1. A LOW
level on MR resets the counter, stops the oscillator and sets the
output buffer in the 3-State condition. MR can be left floating since
an internal pull-up resistor will make the MR inactive. In the HCT
version, the MR input and the two mode select pins S1 and S2 are
TTL compatible, but the X1 input has CMOS input switching levels
and may be driven by a TTL output using a pull-up resistor
connected to V
CC
.
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
°
C, t
r
= t
f
= 6ns
SYMBOL
PARAMETER
CONDITIONS
T
amb
= 25
°
C; GND = 0V
TYPICAL
UNIT
HC
HCT
t
PLH
t
PHL
Propagation delay
X1 to OUT (S1 = S2 = LOW)
C
L
= 50pF; V
CC
= 5V
8
8
ns
f
max
Maximum clock frequency
150
150
MHz
C
I
Input capacitance except X1 and X2
3.5
3.5
pF
C
PD
Power dissipation
capacitance per package
pF
NOTES:
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
= (C
PD
V
CC2
f
I
) + (C
L
+ V
CC2
where:
f
I
= inputfrequency in MHz..
f
O
= output frequency in MHz.
V
CC
= Supply voltage in V.
C
L
= Output load capacitance in pF.
I
pull-up
= Pull-up currents in
μ
A.
For HC and HCT an external clock is applied to X1 with:
t
r
= t
f
6ns, V
I
is GND to V
CC
, MR = HIGH.
I
pull-up
is the summation of –I
I
(
μ
A) of S1 and S2 inputs at the LOW state.
f
O
) + (I
pull-up
V
CC
)
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER NUMBER
DWG NUMBER
8-Pin Plastic SO
0
°
C to +70
°
C
74HC/HCT9323A D
SOT96-1
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