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參數(shù)資料
| 型號： | 74HC85PW,112 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 2/9頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC COMPARATOR MAGNITUDE 16TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Logic Packages |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 系列： | 74HC |
| 類型： | 幅值比較器 |
| 位數(shù)： | 4 |
| 輸出： | 高有效 |
| 輸出功能： | A<B，A=B，A>B |
| 電源電壓： | 2 V ~ 6 V |
| 輸出電流高，低： | 5.2mA，5.2mA |
| 額定電壓和最大 CL 時的最大傳播延遲： | 33ns @ 6V，50pF |
| 電流 - 靜態(tài)： | 8µA |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 安裝類型： | 表面貼裝 |
| 包裝： | 管件 |
| 其它名稱： | 74HC85PW 74HC85PW-ND 935189180112 |
December 1990
2
Philips Semiconductors
Product specication
4-bit magnitude comparator
74HC/HCT85
FEATURES
Serial or parallel expansion without extra gating
Magnitude comparison of any binary words
Output capability: standard
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT85 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT85 are 4-bit magnitude comparators that
can be expanded to almost any length. They perform
comparison of two 4-bit binary, BCD or other monotonic
codes and present the three possible magnitude results at
the outputs (QA>B, QA=B and QA<B). The 4-bit inputs are
weighted (A0 to A3 and B0 to B3), where A3 and B3 are the
most significant bits.
The operation of the “85” is described in the function table,
showing all possible logic conditions. The upper part of the
table describes the normal operation under all conditions
that will occur in a single device or in a series expansion
scheme. In the upper part of the table the three outputs are
mutually exclusive. In the lower part of the table, the
outputs reflect the feed forward conditions that exist in the
parallel expansion scheme.
For proper compare operation the expander inputs (IA>B,
IA=B and IA<B) to the least significant position must be
connected as follows: IA<B =IA>B = = LOW and
IA=B = HIGH.
For words greater than 4-bits, units can be cascaded by
connecting outputs QA<B, QA>Β and QA=B to the
corresponding inputs of the significant comparator.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf = 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPHL/ tPLH
propagation delay
CL = 15 pF; VCC =5 V
An, Bn to QA>B, QA<B
20
22
ns
An, Bn to QA=B
18
20
ns
IA<B,, IA=B, IA>B to QA<B, QA>B
15
ns
IA=B to QA=B
11
15
ns
CI
input capacitance
3.5
pF
CPD
power dissipation capacitance per package
notes 1 and 2
18
20
pF
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