參數(shù)資料
型號(hào): 74HC7731
廠商: NXP Semiconductors N.V.
英文描述: Quad 64-bit static shift register
中文描述: 四路64位靜態(tài)移位寄存器
文件頁數(shù): 8/8頁
文件大?。?/td> 49K
代理商: 74HC7731
September 1993
8
Philips Semiconductors
Product specification
Quad 64-bit static shift register
74HC/HCT7731
Fig.6 C
PD
as a function of the duty factor.
handbook, halfpage
CPD
(pF)
0
0.2
0.4
0.6
duty factor
40
20
0
MLA166
POWER DISSIPATION INFORMATION
The power dissipation per register operating at the same
frequency is given by:
P
D
= (C
PD
x V
CC2
x f
i
) + (C
L
+ V
CC2
x f
o
) + (I
pull-up
x V
CC
)
As P
D
also depends on the frequency at which the
contents of the internal bits are changing, the value of C
PD
is a function of the duty factor (d
f
) being the ration between
data and clock frequency, see Fig.6.
Example:
As the maximum allowable power dissipation in an SO
package at T
amb
= 125
°
C is 60 mW, it is allowed to apply
4 registers at the same time under these conditions.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
f
i
f
o
C
L
V
CC
= clock input frequency
= data output frequency
= output load capacitance in pF
= power supply voltage in V.
f
i
f
o
C
L
V
CC
d
f
C
PD
P
D
= (42.5
×
5
2
×
12) + (25
×
5
2
×
3) = 14625
μ
W
= 12 MHz
= 3 MHz
= 25 pF
= 5 V
= 3/12 = 0.25
= 42.5 pF
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