參數(shù)資料
型號: 74HC74DR2G
廠商: ON SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: Dual D Flip−Flop with Set and Reset High−Performance Silicon−Gate CMOS
中文描述: HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
封裝: LEAD FREE, SOIC-14
文件頁數(shù): 3/8頁
文件大?。?/td> 143K
代理商: 74HC74DR2G
74HC74
http://onsemi.com
3
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Symbol
V
IH
Parameter
Test Conditions
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
|
20 A
V
CC
(V)
2.0
3.0
4.5
6.0
Guaranteed Limit
– 55 to
25 C
1.5
2.1
3.15
4.2
Unit
V
85 C
1.5
2.1
3.15
4.2
125 C
1.5
2.1
3.15
4.2
Minimum High
Level Input
Voltage
V
IL
Maximum Low
Level Input
Voltage
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
|
20 A
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
V
OH
Minimum High
Level Output
Voltage
V
in
= V
IH
or V
IL
|I
out
|
20 A
2.0
4.5
6.0
3.0
4.5
6.0
1.9
4.4
5.9
2.48
3.98
5.48
1.9
4.4
5.9
2.34
3.84
5.34
1.9
4.4
5.9
2.2
3.7
5.2
V
V
in
= V
IH
or V
IL
|I
out
|
|I
out
|
|I
out
|
2.4 mA
4.0 mA
5.2 mA
V
OL
Maximum Low
Level Output
Voltage
V
in
= V
IH
or V
IL
|I
out
|
20 A
2.0
4.5
6.0
3.0
4.5
6.0
6.0
6.0
0.1
0.1
0.1
0.26
0.26
0.26
±
0.1
2.0
0.1
0.1
0.1
0.33
0.33
0.33
±
1.0
20
0.1
0.1
0.1
0.4
0.4
0.4
±
1.0
80
V
V
in
= V
IH
or V
IL
|I
out
|
|I
out
|
|I
out
|
2.4 mA
4.0 mA
5.2 mA
I
in
I
CC
Maximum Input Leakage Current
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
V
in
= V
CC
or GND
I
out
= 0 A
A
A
NOTE:Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High
Speed CMOS Data Book
(DL129/D).
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns)
Symbol
f
max
Parameter
V
CC
(V)
Guaranteed Limit
– 55 to
25 C
Unit
MHz
85 C
4.8
10
24
28
125 C
4.0
8.0
20
24
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
3.0
4.5
6.0
6.0
15
30
35
t
PLH
,
t
PHL
Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)
2.0
3.0
4.5
6.0
100
75
20
17
125
90
25
21
150
120
30
26
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Set or Reset to Q or Q
(Figures 2 and 4)
2.0
3.0
4.5
6.0
105
80
21
18
130
95
26
22
160
130
32
27
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
3.0
4.5
6.0
75
30
15
13
10
95
40
19
16
10
110
55
22
19
10
ns
C
in
Maximum Input Capacitance
NOTE:For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High
Speed CMOS Data Book (DL129/D).
pF
C
PD
Power Dissipation Capacitance (Per Flip
Flop)*
* Used to determine the no
load dynamic power consumption: P
D
= C
PD
V
CC2
f + I
CC
V
CC
. For load considerations, see Chapter 2 of the
ON Semiconductor High
Speed CMOS Data Book (DL129/D).
Typical @ 25
°
C, V
CC
= 5.0 V
32
pF
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