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參數(shù)資料
| 型號： | 74HC7403 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 4-Bit x 64-word FIFO register; 3-state |
| 中文描述： | 4位× 64字的FIFO寄存器，三態(tài) |
| 文件頁數(shù)： | 24/28頁 |
| 文件大?。?/td> | 163K |
| 代理商： | 74HC7403 |
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September 1993
24
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
Expanded format
Figure 20 shows two cascaded FIFOs
providing a capacity of 128 words x
4 bits. Figure 21 shows the signals on
the nodes of both FIFOs after the
application of a SI pulse, when both
FIFOs are initially empty. After a
ripple through delay, data arrives at
the output of FIFO
A
. Due to SO
A
being HIGH, a DOR
A
pulse is
generated. The requirements of SI
B
and D
nB
are satisfied by the DOR
A
pulse width and the timing between
the rising edge of DOR
A
and Q
nA
.
After a second ripple through delay,
data arrives at the output of FIFO
B
.
Figure 22 shows the signals on the
nodes of both FIFOs after the
application of aSO
B
pulse, when both
FIFOs are initially full. After a
bubble-up delay a DIR
B
pulse is
generated, which acts as aSO
A
pulse
for FIFO
A
. One word is transferred
from the output of FIFO
A
to the input
of FIFO
B
. The requirements of the
SO
A
pulse for FIFO
A
is satisfied by
the pulse width of DOR
B
. After a
second bubble-up delay an empty
space arrives at D
nA
, at which time
DIR
A
goes HIGH. Figure 23 shows
the waveforms at all external nodes of
both FIFOs during a complete shift-in
and shift-out sequence.
Note to
Fig.20
The “7403” is easily cascaded to increase word capacity without any external circuitry. In cascaded format, all necessary
communications are handled by the FIFOs. Figures 21 and 22 demonstrate the intercommunication timing between
FIFO
A
and FIFO
B
. Figure 23 provides an overview of pulses and timing of two cascaded FIFOs, when shifted full and
shifted empty again.
Fig.20 Cascading for increased word capacity; 128 words x 4 bits.
MGA679
DIR
OE
SI
MR
DnA
4
DIR
SI
DOR
SO
DATA INPUT
A
A
4
SOA
DORA
QnA
7403
FIFO A
DIR
OE
SI
MR
DnB
B
B
4
SOB
QnB
DORB
7403
FIFO B
DATA OUTPUT
OE
MR
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74HC7403D | 功能描述:寄存器 4-BIT X64 WORD FIFO REG 3-ST RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| 74HC7403D,512 | 功能描述:寄存器 4-BIT X64 WORD FIFO RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| 74HC7403D,518 | 功能描述:寄存器 4-BIT X64 WORD FIFO RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| 74HC7403D-Q100,518 | 制造商:NXP Semiconductors 功能描述:FIFO Register Single 4-CH CMOS 16-Pin SO T/R 制造商:NXP Semiconductors 功能描述:74HC7403D-Q100/SO16/REEL13DP// - Tape and Reel 制造商:NXP Semiconductors 功能描述:IC FIFO REGISTER 4X64 3ST 16SOIC |
| 74HC7403D-T | 功能描述:寄存器 4-BIT X64 WORD FIFO REG 3-ST RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
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