參數(shù)資料
型號(hào): 74HC643
廠商: NXP Semiconductors N.V.
英文描述: Octal bus transceiver; 3-state; true/inverting
中文描述: 八路總線收發(fā)器,三態(tài);真/反相
文件頁數(shù): 2/6頁
文件大?。?/td> 52K
代理商: 74HC643
December 1990
2
Philips Semiconductors
Product specification
Octal bus transceiver; 3-state;
true/inverting
74HC/HCT643
FEATURES
Octal bidirectional bus interface
True and inverting 3-state outputs
Output capability: bus driver
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT643 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT643 are octal transceivers featuring true
and inverting 3-state bus compatible outputs in both send
and receive directions.
The “643” features an output enable (OE) input for easy
cascading and a send/receive (DIR) for direction control.
OE controls the outputs so that the buses are effectively
isolated.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
2.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/
tPLH
propagation delay
A
n
to B
n
; inverting
B
n
to A
n
; true
input capacitance
input/output capacitance
power dissipation capacitance per transceiver notes 1 and 2
C
L
= 15 pF; V
CC
= 5 V
7
8
3.5
10
42
8
11
3.5
10
44
ns
ns
pF
pF
pF
C
I
C
I/O
C
PD
相關(guān)PDF資料
PDF描述
74HCT646D Octal bus transceiver/register; 3-state
74HC646 Octal bus transceiver/register; 3-state
74HC646D Octal bus transceiver/register; 3-state
74HC646DB Octal bus transceiver/register; 3-state
74HC646N Octal bus transceiver/register; 3-state
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