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參數(shù)資料
| 型號： | 74HC4543 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | BCD to 7-segment latch/decoder/driver for LCDs |
| 中文描述： | BCD碼至7段鎖存器/解碼器/驅(qū)動器的液晶顯示器 |
| 文件頁數(shù)： | 2/11頁 |
| 文件大?。?/td> | 78K |
| 代理商： | 74HC4543 |
December 1990
2
Philips Semiconductors
Product specification
BCD to 7-segment latch/decoder/driver
for LCDs
74HC/HCT4543
FEATURES
Latch storage of BCD inputs
Blanking inputs
Output capability: non-standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4543 are high-speed Si-gate CMOS
devices and are pin compatible with “4543” of the “4000B”
series. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT4543 are BCD to 7-segment
latch/decoder/drivers for liquid crystal displays. They have
four address inputs (D
0
to D
3
), an active HIGH latch
disable input (LD), an active HIGH blanking input (BI), an
active HIGH phase input (PH) and seven buffered
segment outputs (Q
a
to Q
g
).
The “4543” provides the function of a 4-bit storage latch
and an 8-4-2-1 BCD to 7-segment decoder driver. The
“4543” can invert the logic levels of the output combination.
The phase (PH), blanking (BI) and latch disable (LD)
inputs are used to reverse the function table phase, blank
the display and store a BCD code, respectively.
For liquid crystal displays a square-wave is applied to PH
and the electrical common back-plane of the display. The
outputs of the “4543” are directly connected to the
segments of the liquid crystal.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
2.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
propagation delay
D
n
to Q
n
LD to Q
n
BI to Q
n
input capacitance
power dissipation capacitance per package
C
L
= 15 pF; V
CC
= 5 V
29
32
20
3.5
42
33
31
28
3.5
42
ns
ns
ns
pF
pF
C
I
C
PD
notes 1 and 2
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