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參數(shù)資料
| 型號(hào)： | 74HC4059N3 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | Programmable divide-by-n counter |
| 中文描述： | HC/UH SERIES, ASYN POSITIVE EDGE TRIGGERED DOWN DIVIDE BY N COUNTER, PDIP24 |
| 封裝： | 0.300 INCH, PLASTIC, SOT-222-1, MS-001AF, DIP-24 |
| 文件頁數(shù)： | 7/20頁 |
| 文件大小： | 147K |
| 代理商： | 74HC4059N3 |
1998 Jul 08
7
Philips Semiconductors
Product specification
Programmable divide-by-n counter
74HC/HCT4059
FUNCTION TABLE
Note
1.
It is recommended that the device is in the master preset mode (K
b
= K
c
= logic 0) in order to correctly initialize the
device prior to start-up. An example of a suitable external circuit is shown in Fig.14.
H = HIGH voltage level
L = LOW voltage level
X = don’t care
Table 1
Table 2
Table 3
LATCH
ENABLE
INPUT
MODE
SELECT
INPUTS
FIRST COUNTING
SECTION
DECADE 1
LAST COUNTING
SECTION
DECADE 5
COUNTER
RANGE
OPERATION
LE
K
a
K
b
K
c
MODE
MAX
PRESET
STATE
JAM
INPUTS
USED
DIVIDED
BY
MAX.
PRESET
STATE
JAM
INPUTS
USED
BCD
MAX.
BINARY
MAX.
H
H
H
H
H
L
L
L
L
L
H
H
L
H
L
H
H
L
H
L
H
L
H
H
L
L
H
H
H
L
L
H
H
H
H
H
H
L
H
H
H
H
L
L
2
4
5
8
10
2
4
5
8
10
10
1
3
4
7
9
1
3
4
7
9
9
J
1
J
1
J
2
J
1
J
2
J
3
J
1
J
2
J
3
J
1
J
2
J
3
J
4
1
J
1
J
1
J
2
J
1
J
2
J
3
J
1
J
2
J
3
J
1
J
2
J
3
J
4
1
J
1
J
2
J
3
J
4
1
8
4
2
2
7
3
1
1
0
7
3
1
1
0
0
J
2
J
3
J
4
J
3
J
4
J
4
J
4
J
2
J
3
J
4
J
3
J
4
J
4
J
4
15 999 17 331
15 999 18 663
9 999 13 329
15 999 21 327
9 999 16 659
15 999 17 331
15 999 18 663
9 999 13 329
15 999 21 327
9 999 16 659
9 999 16 659
fixed
10 000
timer mode
8
4
2
2
divide-by-n mode
L
L
H
L
preset inhibited
preset inhibited
divide-by-10 000
mode
master preset
mode
X
X
L
L
master preset
master preset
4
1
5
9
6
J
1
L
J
2
L
J
3
H
J
4
H
J
5
H
J
6
L
J
7
H
J
8
L
J
9
H
J
10
L
J
11
L
J
12
H
J
13
L
J
14
H
J
15
H
J
16
L
6
1
7
4
5
J
1
L
J
2
H
J
3
H
J
4
H
J
5
H
J
6
H
J
7
H
J
8
L
J
9
L
J
10
L
J
11
H
J
12
L
J
13
H
J
14
L
J
15
H
J
16
L
9
7
4
8
J
1
H
J
2
L
J
3
L
J
4
H
J
5
H
J
6
H
J
7
H
J
8
L
J
9
L
J
10
L
J
11
H
J
12
L
J
13
L
J
14
L
J
15
L
J
16
H
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