參數(shù)資料
型號: 74HC374
廠商: NXP Semiconductors N.V.
英文描述: Octal D-type flip-flop; positive edge-trigger; 3-state
中文描述: 八路D型觸發(fā)器,上升沿觸發(fā),三態(tài)
文件頁數(shù): 2/8頁
文件大?。?/td> 60K
代理商: 74HC374
December 1990
2
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive
edge-trigger; 3-state
74HC/HCT374
FEATURES
3-state non-inverting outputs for bus oriented
applications
8-bit positive, edge-triggered register
Common 3-state output enable input
Independent register and 3-state buffer operation
Output capability: bus driver
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT374 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT374 are octal D-type flip-flops featuring
separate D-type inputs for each flip-flop and 3-state
outputs for bus oriented applications. A clock (CP) and an
output enable (OE) input are common to all flip-flops.
The 8 flip-flops will store the state of their individual
D-inputs that meet the set-up and hold times requirements
on the LOW-to-HIGH CP transition.
When OE is LOW, the contents of the 8 flip-flops are
available at the outputs. When OE is HIGH, the outputs go
to the high impedance OFF-state. Operation of the
OE input does not affect the state of the flip-flops.
The “374” is functionally identical to the “534”, but has
non-inverting outputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
2.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
f
max
C
I
C
PD
propagation delay CP to Q
n
maximum clock frequency
input capacitance
power dissipation capacitance per flip-flop
C
L
= 15 pF; V
CC
= 5 V
15
77
3.5
17
13
48
3.5
17
ns
MHz
pF
pF
notes 1 and 2
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