參數(shù)資料
型號(hào): 74HC283
廠商: NXP Semiconductors N.V.
英文描述: 4-bit binary full adder with fast carry
中文描述: 4位二進(jìn)制全加器快速進(jìn)行
文件頁(yè)數(shù): 8/8頁(yè)
文件大?。?/td> 61K
代理商: 74HC283
December 1990
8
Philips Semiconductors
Product specification
4-bit binary full adder with fast carry
74HC/HCT283
AC WAVEFORMS
Fig.6
Waveforms showing the inputs (C
IN
, A
n
, B
n
)
to the outputs (
n
, C
OUT
) propagation delays
and the output transition times.
(1) HC : V
M
= 50%; V
I
= GND to V
CC
.
HCT: V
M
= 1.3 V; V
I
= GND to 3 V.
APPLICATION INFORMATION
Fig.7 3-bit adder.
Fig.8 2-bit and 1-bit adder.
Fig.9 5-input encoder.
Fig.10 5-input majority gate.
Notes to Figs
7
to
10
Figure 7 shows a 3-bit adder using the “283”. Tying the
operand inputs of the fourth adder (A
3
, B
3
) LOW makes
3
dependent on, and equal to, the carry from the third adder.
Based on the same principle, Figure 8 shows a method of
dividing the “283” into a 2-bit and 1-bit adder. The third
stage adder (A
2
, B
2
,
2
) is used simply as means of
transferring the carry into the fourth stage (via A
2
and B
2
)
and transferring the carry from the second stage on
2
.
Note that as long as long as A
2
and B
2
are the same, HIGH
or LOW, they do not influence
2
. Similarly, when A
2
and
B
2
are the same, the carry into the third stage does not
influence the carry out of the third stage. Figure 9 shows a
method of implementing a 5-input encoder, where the
inputs are equally weighted. The outputs
0
,
1
and
2
produce a binary number equal to the number inputs (I
1
to
I
5
) that are HIGH. Figure 10 shows a method of
implementing a 5-input majority gate. When three or more
inputs (I
1
to I
5
) are HIGH, the output M
5
is HIGH.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
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