參數(shù)資料
型號(hào): 74HC273PW,112
廠(chǎng)商: NXP Semiconductors
文件頁(yè)數(shù): 2/21頁(yè)
文件大小: 0K
描述: IC OCTAL D F-F POS-EDGE 20TSSOP
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 1,875
系列: 74HC
功能: 主復(fù)位
類(lèi)型: D 型總線(xiàn)
輸出類(lèi)型: 非反相
元件數(shù): 1
每個(gè)元件的位元數(shù): 8
頻率 - 時(shí)鐘: 122MHz
延遲時(shí)間 - 傳輸: 13ns
觸發(fā)器類(lèi)型: 正邊沿
輸出電流高,低: 5.2mA,5.2mA
電源電壓: 2 V ~ 6 V
工作溫度: -40°C ~ 125°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
包裝: 管件
74HC_HCT273
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 10 June 2013
10 of 21
NXP Semiconductors
74HC273; 74HCT273
Octal D-type flip-flop with reset; positive-edge trigger
11. Waveforms
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7.
Propagation delay clock input (CP) to output (Qn), clock (CP) pulse width, output transition time and the
maximum clock pulse frequency
001aae062
CP input
Qn output
tPHL
tPLH
tW
VM
10%
90%
VOH
VI
GND
VOL
VM
1/fmax
tTHL
tTLH
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8.
Propagation delay master reset (MR) to output (Qn), pulse width master reset (MR) and recovery time
master reset (MR) to clock (CP)
mna464
MR input
CP input
Qn output
tPHL
tW
trec
VM
VI
GND
VI
VOL
GND
VM
VOH
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