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參數(shù)資料
| 型號(hào)： | 74HC1G32GV,125 |
| 廠商： | NXP Semiconductors |
| 文件頁(yè)數(shù)： | 6/11頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC 2-INPUT OR GATE SC74A-5 |
| 產(chǎn)品培訓(xùn)模塊： | Logic Packages |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 系列： | 74HC |
| 邏輯類(lèi)型： | 或門(mén) |
| 電路數(shù)： | 1 |
| 輸入數(shù)： | 2 |
| 電源電壓： | 2 V ~ 6 V |
| 電流 - 靜態(tài)（最大值）： | 20µA |
| 輸出電流高，低： | 2.6mA，2.6mA |
| 邏輯電平 - 低： | 0.5 V ~ 1.8 V |
| 邏輯電平 - 高： | 1.5 V ~ 4.2 V |
| 額定電壓和最大 CL 時(shí)的最大傳播延遲： | 23ns @ 6V，50pF |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 供應(yīng)商設(shè)備封裝： | 5-TSOP |
| 封裝/外殼： | SC-74A，SOT-753 |
| 包裝： | 帶卷 (TR) |
2005 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FST3125 Rev. 1.0.3
4
FST3125
—
4-
B
it
B
u
s
Swit
ch
DC Electrical Characteristics
Typical values are at VCC = 5.0V and TA = 25°C.
TA=-40 to +85°C
Symbol
Parameter
Conditions
VCC (V)
Min.
Typ.
Max.
Units
VIK
Clamp Diode Voltage
IIN = -18mA
4.5
-1.2
V
VIH
High-Level Input Voltage
4.0 to 5.5
2.0
V
VIL
Low-Level Input Voltage
4.0 to 5.5
0.8
V
IIN
Input Leakage Current
0
≤ V
IN ≤ 5.5
5.5
±1.0
A
IOZ
Off-state Leakage
Current
0
≤ A, B ≤ V
CC
5.5
±1.0
A
VIN = 0V, IIN = 64mA
4.5
4
7
VIN = 0V, IIN = 30mA
4.5
4
7
VIN = 2.4V, IIN = 15mA
4.5
8
15
RON
Switch On Resistance
(3)
VIN = 2.4V, IIN = 15mA
4.0
11
20
Ω
ICC
Quiescent Supply Current
VIN = VCC or GND,
IOUT = 0
5.5
3
A
ΔI
CC
Increase in ICC per Input
One Input at 3.4V, Other
Inputs at VCC or GND
5.5
2.5
mA
Note:
3.
Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance
is determined by the lower of the voltages on the A or B pins.
AC Electrical Characteristics
TA = -40 to +85°C, CL = 50pF, and RU = RD = 500Ω.
VCC = 4.5 – 5.5V
VCC = 4.0V
Symbol
Parameter
Conditions
Min.
Max.
Min.
Max.
Units
Figure
tPHL, tPLH
Propagation Delay
Bus-to-Bus
(4)
VIN = Open
0.25
ns
Figure 4
Figure 5
tPZH ,tPZL
Output Enable Time
VIN = 7V for tPZL
VIN = Open for
tPZH
1.0
5.0
5.5
ns
Figure 4
Figure 5
tPHZ, tPLZ
Output Disable Time
VIN = 7V for tPLZ
VIN = Open for
tPHZ
1.5
5.3
5.6
ns
Figure 4
Figure 5
Note:
4.
This parameter is guaranteed by design, but is not tested. The bus switch contributes no propagation delay
other than the RC delay of the typical on resistance of the switch and the 50pF load capacitance when driven by
an ideal voltage source (zero output impedance).
Capacitance
TA = +25°C, f = 1MHz. Capacitance is characterized, but not tested.
Symbol
Parameter
Conditions
Typ.
Units
CIN
Control Pin Input Capacitance
VCC = 5.0V
3
pF
CI/O
Input/Output Capacitance
VCC, /OE = 5.0V
2
pF
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