參數(shù)資料
型號: 74HC193PW,112
廠商: NXP Semiconductors
文件頁數(shù): 13/30頁
文件大?。?/td> 0K
描述: IC 4BIT BINARY UP/DN CNT 16TSSOP
產品培訓模塊: Logic Packages
標準包裝: 96
系列: 74HC
邏輯類型: 二進制計數(shù)器
方向: 上,下
元件數(shù): 1
每個元件的位元數(shù): 4
復位: 異步
計時: 同步
計數(shù)速率: 49MHz
觸發(fā)器類型: 正邊沿
電源電壓: 2 V ~ 6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 16-TSSOP
包裝: 管件
其它名稱: 74HC193PW
74HC193PW-ND
935188980112
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 24 June 2013
20 of 30
NXP Semiconductors
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Table 10.
Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
Fig 13. The data input (Dn) to parallel load input (PL) set-up and hold times
001aag417
Dn input
Qn output
VOL
VOH
GND
VI
GND
VI
PL input
VM
tsu
th
VM
tsu
th
Measurement points are given in Table 10.
tPLH and tPHL are the same as tpd.
Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
Fig 14. The data input (Dn), parallel load input (PL) and the master reset input (MR) to the terminal count outputs
(TCU,TCD) propagation delays
001aag418
PL, MR, Dn
input
TCU, TCD
output
tPLH
tPHL
VM
VOL
VOH
GND
VI
Measurement points are given in Table 10.
Fig 15. The CPU to CPD or CPD to CPU hold times
001aag419
CPD or CPU
input
CPU or CPD
input
VI
GND
VI
GND
VM
th
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