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參數(shù)資料
| 型號： | 74HC181D-T |
| 英文描述： | SC70/µDFN, Single/Dual Low-Voltage, Low-Power µP Reset Circuits |
| 中文描述： | ALU的不動點(diǎn) |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 78K |
| 代理商： | 74HC181D-T |
2002 May 15
7
Philips Semiconductors
Product specification
Bus buffer/line driver; 3-state
74HC1G126; 74HCT1G126
AC CHARACTERISTICS
Type 74HC1G
GND = 0 V; t
r
= t
f
≤
6.0 ns; C
L
= 50 pF.
Note
1.
All typical values are measured at T
amb
= 25
°
C.
Type 74HCT1G
GND = 0 V; t
r
= t
f
≤
6.0 ns; C
L
= 50 pF.
Note
1.
All typical values are measured at T
amb
= 25
°
C.
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
(
°
C)
UNIT
WAVEFORMS
V
CC
(V)
40 to +85
40 to +125
MIN.
TYP.
(1)
MAX.
MIN.
MAX.
t
PHL
/t
PLH
propagation
delay A to Y
see Figs 5 and 7
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
24
10
9
24
10
8
16
12
11
125
25
21
155
31
26
155
31
26
150
30
26
190
38
32
190
38
32
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
PZH
/t
PZL
3-state output
enable time
OE to Y
see Figs 6 and 7
t
PHZ
/t
PLZ
3-state output
disable time
OE to Y
see Figs 6 and 7
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
(
°
C)
UNIT
WAVEFORMS
V
CC
(V)
40 to +85
40 to +125
MIN.
TYP.
(1)
MAX.
MIN.
MAX.
t
PHL
/t
PLH
propagation
delay A to Y
3-state output
enable time
OE to Y
3-state output
disable time
OE to Y
see Figs 5 and 7
4.5
11
30
36
ns
t
PZH
/t
PZL
see Figs 6 and 7
4.5
10
35
42
ns
t
PHZ
/t
PLZ
see Figs 6 and 7
4.5
12
31
38
ns
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