參數(shù)資料
型號: 74HC139
廠商: NXP Semiconductors N.V.
英文描述: Dual 2-to-4 line decoder/demultiplexer
中文描述: 雙路2至4線譯碼器/解復(fù)用器
文件頁數(shù): 2/7頁
文件大?。?/td> 44K
代理商: 74HC139
September 1993
2
Philips Semiconductors
Product specification
Dual 2-to-4 line decoder/demultiplexer
74HC/HCT139
FEATURES
Demultiplexing capability
Two independent 2-to-4 decoders
Multifunction capability
Active LOW mutually exclusive outputs
Output capability: standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT139 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). It is specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT139 are high-speed, dual 2-to-4 line
decoder/multiplexers. This device has two independent
decoders, each accepting two binary weighted inputs
(nA
0
and nA
1
) and providing four mutually exclusive active
LOW outputs (nY
0
to nY3). Each decoder has an active
LOW enable input (nE).
When nE is HIGH, every output is forced HIGH. The
enable can be used as the data input for a 1-to-4
demultiplexer application.
The “139” is identical to the HEF4556 of the HE4000B
family.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
2.
APPLICATIONS
Memory decoding or data-routing
Code conversion
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
propagation delay
nA
n
to nY
n
nE
3
to nY
n
input capacitance
power dissipation capacitance per multiplexer
C
L
= 15 pF; V
CC
= 5 V
11
10
3.5
42
13
13
3.5
44
ns
ns
pF
pF
C
I
C
PD
notes 1 and 2
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