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參數(shù)資料
| 型號： | 74FST6800DWR2 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | 10−Bit Bus Switch with Precharged Outputs |
| 中文描述： | CBT/FST/QS/5C/B SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24 |
| 封裝： | SOIC-24 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 203K |
| 代理商： | 74FST6800DWR2 |
74FST6800
http://onsemi.com
3
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
Supply Voltage
Operating, Data Retention Only
4.0
5.5
V
V
I
Input Voltage
(Note 5)
0
5.5
V
V
O
Output Voltage
(HIGH or LOW State)
0
5.5
V
T
A
Operating Free
Air Temperature
40
85
°
C
t/ V
Input Transition Rise or Fall Rate
Switch I/O
Switch Control Input
V
CC
= 5.0 V
0.5 V
0
DC
5
ns/V
5. Unused control inputs may not be left open. All control inputs must be tied to a high or low logic input voltage level.
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
V
CC
(V)
T
A
=
40 C to
85 C
Unit
Min
Typ*
Max
V
IK
Clamp Diode Resistance
I
IN
=
18mA
4.5
1.2
V
V
IH
High
Level Input Voltage
4.0 to 5.5
2.0
V
V
IL
Low
Level Input Voltage
4.0 to 5.5
0.8
V
I
I
Input Leakage Current
0
V
IN
5.5 V
5.5
1.0
A
I
OZ
OFF
STATE Leakage Current
0
A, B
V
CC
5.5
1.0
A
R
ON
Switch On Resistance (Note 6)
V
IN
= 0 V, I
IN
= 64 mA
4.5
4
7
V
IN
= 0 V, I
IN
= 30 mA
4.5
4
7
V
IN
= 2.4 V, I
IN
= 15 mA
4.5
8
15
V
IN
= 2.4 V, I
IN
= 15 mA
4.0
11
20
I
CC
Quiescent Supply Current
V
IN
= V
CC
or GND, I
OUT
= 0
5.5
3
A
I
CC
Increase In I
CC
per Input
*Typical values are at V
CC
= 5.0 V and T
A
= 25
°
C.
6. Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower
of the voltages on the two (A or B) pins.
One input at 3.4 V, Other inputs at V
CC
or GND
5.5
2.5
mA
AC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
T
A
=
40 C to
85 C
C
L
= 50 pF, RU = RD = 500
Unit
V
CC
= 4.5
5.5 V
V
CC
= 4.0 V
Min
Max
Min
Max
t
PHL
,
t
PLH
Prop Delay Bus to Bus (Note 7)
V
I
= OPEN
0.25
0.25
ns
t
PZH
,
t
PZL
Output Enable Time, I
OE
to Bus A, B
Bias V = GND
V
I
= OPEN for t
PZH
1.0
5.1
5.6
ns
t
PHZ
,
t
PLZ
Output Disable Time, I
OE
to Bus A, B
Bias V = GND
V
I
= OPEN for t
PHZ
1.0
5.5
5.5
ns
7. This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the
typical On resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance).
CAPACITANCE
(Note 8)
Symbol
Parameter
Conditions
Typ
Max
Unit
C
IN
Control Pin Input Capacitance
V
CC
= 5.0 V
3
pF
C
I/O
A/B Port Input/Output Capacitance
V
CC
, OE = 5.0 V
5
pF
8. T
A
=
25
°
C, f = 1 MHz, Capacitance is characterized but not tested.
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