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參數(shù)資料
| 型號： | 74F8961 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Octal latched bidirectional Futurebus transceivers 3-State open-collector |
| 中文描述： | 八進制鎖存雙向Futurebus收發(fā)器三態(tài)開路集電極 |
| 文件頁數(shù)： | 11/11頁 |
| 文件大?。?/td> | 194K |
| 代理商： | 74F8961 |
Philips Semiconductors FAST Products
Product specification
74F8960/74F8961
Octal latched bidirectional Futurebus transceivers
(3-State + open-collector)
December 19, 1990
11
AC WAVEFORMS
V
M
V
M
V
M
V
M
Waveform 1. Propagation delay for data to output
Waveform 3. Data setup and hold times and LE pulse width
Waveform 4. 3–state output enable time to high level
and output disable time from high level
Waveform 5. 3-state output enable time to low level
and output disable time from low level
LE
V
M
V
M
V
M
V
M
V
M
V
M
t
s
(L)
t
s
(H)
t
h
(L)
t
h
(H)
V
M
V
M
V
M
t
PHZ
t
PZH
V
OH
-0.3V
0V
V
M
V
M
V
M
t
PLZ
t
PZL
V
OL
+0.3V
OEA
An
OEA
An
An
An, Bn
An, Bn, OEBn
t
PLH
t
PHL
V
M
t
w
(L)
V
M
V
M
V
M
V
M
Waveform 2. Propagation delay for data to output
An, Bn
An, Bn, OEBn
t
PHL
t
PLH
NOTES:
1. For all waveforms, V
= 1.5V.
2. The shaded areas indicate when the input is permitted to change for predictable output performance.
TEST CIRCUITS AND WAVEFORMS
C
D
t
w
90%
V
M
10%
90%
V
M
10%
90%
V
M
10%
90%
V
M
10%
NEGATIVE
PULSE
POSITIVE
PULSE
t
w
AMP (V)
Low V
Low V
t
THL (
t
f
)
INPUT PULSE REQUIREMENTS
rep. rate
t
w
t
TLH
t
THL
Input pulse definition
V
CC
family
74F
D.U.T.
PULSE
GENERATOR
R
L
C
L
R
T
V
IN
V
OUT
Test circuit for 3–state outputs on A port
DEFINITIONS:
R
L
=
C
L
=
R
U
=
C
D
=
R
T
=
Load resistor; see AC electrical characteristics for value.
Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value.
Pull up resistor; see AC electrical characteristics for value.
Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value.
Termination resistance should be equal to Z
OUT
of pulse generators.
t
THL (
t
f
)
t
TLH (
t
r
)
t
TLH (
t
r
)
AMP (V)
amplitude
V
M
R
L
7.0V
V
CC
D.U.T.
PULSE
GENERATOR
R
T
V
IN
V
OUT
Test circuit for outputs on B port
R
U
7.0V
Low V
SWITCH POSITION
TEST
t
PLZ
, t
PZL
SWITCH
closed
open
All other
A port
3.0V
0.0V
1.5V
1MHz
500ns
2.5ns
2.5ns
B port
3.0V
1.0V
1.5V
1MHz
500ns
4.0ns
4.0ns
相關PDF資料 |
PDF描述 |
|---|---|
| 74F8960 | Octal latched bidirectional Futurebus transceivers(3-State + open-collector)(八鎖存雙向預置總線收發(fā)器（三態(tài)+開啟集電極）) |
| 74F8962 | 9-Bit latched bidirectional Futurebus transceivers open-collector |
| 74F8963 | 9-Bit latched bidirectional Futurebus transceivers open-collector |
| 74F8965 | 9-Bit address/data Futurebus transceiver, ADT |
| 74F8966 | 9-Bit address/data Futurebus transceiver, ADT |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 74F8962 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:9-Bit latched bidirectional Futurebus transceivers open-collector |
| 74F8963 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:9-Bit latched bidirectional Futurebus transceivers open-collector |
| 74F8965 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:9-Bit address/data Futurebus transceiver, ADT |
| 74F8966 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:9-Bit address/data Futurebus transceiver, ADT |
| 74F899 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:9-Bit Latchable Transceiver with Parity Generator/Checker |
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