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參數(shù)資料
| 型號(hào)： | 74F85 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 4-bit magnitude comparator(4位等值比較器) |
| 中文描述： | 4位數(shù)值比較（4位等值比較器） |
| 文件頁(yè)數(shù)： | 2/10頁(yè) |
| 文件大?。?/td> | 86K |
| 代理商： | 74F85 |
Philips Semiconductors
Product specification
74F85
4-bit magnitude comparator
2
September 27, 1994
853–0055 13903
FEATURES
High-impedance NPN base inputs for reduced loading
(20
μ
A in High and Low states)
Magnitude comparison of any binary words
Serial or parallel expansion without extra gating
DESCRIPTION
The 74F85 is a 4-bit magnitude comparator that can be expanded to
almost any length. It compares two 4-bit binary, BCD, or other
monotonic codes and presents the three possible magnitude results
at the outputs. The 4-bit inputs are weighted (A0–A3) and (B0–B3)
where A3 and B3 are the most significant bits. The operation of the
74F85 is described in the Function Table, showing all possible logic
conditions. The upper part of the table describes the normal
operation under all conditions that will occur in a single device or in
a series expansion scheme. In the upper part of the table the three
outputs are mutually exclusive. In the lower part of the table, the
outputs reflect the feed-forward conditions that exist in the parallel
expansion scheme. The expansion inputs I
A>B
, and I
A=B
and I
A<B
are the least significant bit positions. When used for series
expansion, the A>B, A=B and A<B outputs of the lease significant
word are connected to the corresponding I
A>B
, I
A=B
and I
A<B
inputs
of the next higher stage. Stages can be added in this manner to any
length, but a propagation delay penalty of about 15ns is added with
each additional stage. For proper operation, the expansion inputs of
the least significant word should be tied as follows: I
A>B
= Low,
I
A=B
= High, and I
A<B
= Low.
PIN CONFIGURATION
16
15
14
13
12
11
10
7
6
5
4
3
2
1
A<B
V
CC
A1
B1
A0
A2
A3
B2
B3
I
A<B
A=B
I
A=B
I
A>B
A>B
9
8
GND
B0
SF00075
TYPE
TYPICAL
PROPAGATION
DELAY
TYPICAL
SUPPLY CURRENT
(TOTAL)
74F85
7.0ns
40mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±
10%,
T
amb
= 0
°
C to +70
°
C
N74F85N
PKG DWG #
16-pin plastic DIP
SOT38-4
16-pin plastic SO
N74F85D
SOT162-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/LOW
LOAD VALUE HIGH/LOW
A0–A3
Comparing inputs
1.0/0.033
20
μ
A/20
μ
A
20
μ
A/20
μ
A
20
μ
A/20
μ
A
B0–B3
Comparing inputs
1.0/0.033
I
A<B
, I
A=B
, I
A>B
A<B, A=B, A>B
NOTE:
One (1.0) FAST unit load is defined as: 20
μ
A in the High state and 0.6mA in the Low state.
Expansion inputs (active High)
1.0/0.033
Data outputs (active High)
50/33
1.0mA/20mA
LOGIC SYMBOL
5
6
7
10
12
13
15
9
11
14
V
= Pin 16
GND = Pin 8
SF00076
1
A0
A1
A2
A3
B0
B1
B2
B3
A>B
A=B
A<B
I
A>B
I
A=B
I
A<B
2
3
4
IEC/IEEE SYMBOL
SF00077
COMP
7
6
5
10
12
13
15
9
11
14
1
2
3
4
0
3
0
3
<
=
>
P<Q
P=Q
P>Q
P
Q
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