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參數(shù)資料
| 型號(hào)： | 74F652 |
| 廠(chǎng)商： | National Semiconductor Corporation |
| 英文描述： | Transceivers/Registers |
| 中文描述： | 收發(fā)器/寄存器 |
| 文件頁(yè)數(shù)： | 4/10頁(yè) |
| 文件大?。?/td> | 188K |
| 代理商： | 74F652 |
Functional Description
In the transceiver mode, data present at the HIGH imped-
ance port may be stored in either the A or B register or both.
The select (SAB, SBA) controls can multiplex stored and
real-time.
The examples inFigure 1 demonstrate the four fundamental
bus-management functions that can be performed with the
Octal bus transceivers and receivers.
Data on the A or B data bus, or both can be stored in the
internal D flip-flop by LOW to HIGH transitions at the appro-
priate Clock Inputs (CPAB, CPBA) regardless of the Select
or Output Enable Inputs. When SAB and SBA are in the real
time transfer mode, it is also possible to store data without
using the internal D flip-flops by simultaneously enabling
OEAB and OEBA. In this configuration each Output reinforc-
es its Input. Thus when all other data sources to the two
sets of bus lines are in a HIGH impedance state, each set of
bus lines will remain at its last state.
Note A: Real-Time
Transfer Bus B to Bus A
TL/F/9581–6
OEAB
OEBA
CPAB
CPBA
SAB
SBA
L
L
X
X
X
L
Note B: Real-Time
Transfer Bus A to Bus B
TL/F/9581–7
OEAB
OEBA
CPAB
CPBA
SAB
SBA
H
H
X
X
L
X
Note C: Storage
TL/F/9581–8
OEAB
OEBA
CPAB
CPBA
SAB
SBA
X
H
L
X
X
X
L
X
X
L
X
X
L
H
L
L
X
X
Note D: Transfer Storage
Data to A or B
TL/F/9581–9
OEAB
OEBA
CPAB
CPBA
SAB
SBA
H
L
H or L
H or L
H
X
FIGURE 1
Inputs
Inputs/Outputs (Note 1)
Operating Mode
OEAB
OEBA
CPAB
CPBA
SAB
SBA
A
0
thru A
7
B
0
thru B
7
L
H
H or L
H or L
X
X
Input
Input
Isolation
L
H
L
L
L
L
X
X
Store A and B Data
X
H
H or L
X
X
Input
Not Specified
Store A, Hold B
H
H
L
L
L
X
X
Input
Output
Store A in Both Registers
L
X
H or L
X
X
Not Specified
Input
Hold A, Store B
L
L
L
X
X
Output
Input
Store B in Both Registers
L
L
X
X
X
L
Output
Input
Real-Time B Data to A Bus
L
L
X
H or L
X
H
Store B Data to A Bus
H
H
X
X
L
X
Input
Output
Real-Time A Data to B Bus
H
H
H or L
X
H
X
Stored A Data to B Bus
H
L
H or L
H or L
H
H
Output
Output
Stored A Data to B Bus and
Stored B Data to A Bus
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
L
e
LOW to HIGH Clock Transition
Note 1:
The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at the
bus pins will be stored on every LOW to HIGH transition on the clock inputs.
4
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| 74F651SPC | Transceivers/Registers |
| 74F652SC | Transceivers/Registers |
| 74F652SPC | Transceivers/Registers |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| 74F652_XDC3026B WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| 74F652A | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Transceivers/registers |
| 74F652SC | 功能描述:總線(xiàn)收發(fā)器 Transceiver/Register RoHS:否 制造商:Fairchild Semiconductor 邏輯類(lèi)型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類(lèi)型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74F652SCX | 功能描述:總線(xiàn)收發(fā)器 Transceiver/Register RoHS:否 制造商:Fairchild Semiconductor 邏輯類(lèi)型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類(lèi)型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74F652SPC | 功能描述:總線(xiàn)收發(fā)器 Transceiver/Register RoHS:否 制造商:Fairchild Semiconductor 邏輯類(lèi)型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類(lèi)型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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