參數(shù)資料
型號: 74F646BSPCQB
廠商: National Semiconductor Corporation
英文描述: Octal Transceiver/Register with TRI-STATE Outputs
中文描述: 八路收發(fā)器/注冊的三態(tài)輸出
文件頁數(shù): 3/12頁
文件大?。?/td> 217K
代理商: 74F646BSPCQB
Unit Loading/Fan Out
54F/74F
Pin Names
Description
U.L.
Input I
IH
/I
IL
Output I
OH
/I
OL
HIGH/LOW
A
0
–A
7
Data Register A Inputs/
TRI-STATE Outputs
Data Register B Inputs/
TRI-STATE Outputs
3.5/1.083
600/106.6 (80)
b
12 mA/64 mA (48 mA)
3.5/1.083
70
m
A/
b
650
m
A
600/106.6 (80)
b
12 mA/64 mA (48 mA)
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
70
m
A/
b
650
m
A
B
0
–B
7
CPAB, CPBA Clock Pulse Inputs
SAB, SBA
Select Inputs
G
Output Enable Input
DIR
Direction Control Input
20
m
A/
b
0.6 mA
20
m
A/
b
0.6 mA
20
m
A/
b
0.6 mA
20
m
A/
b
0.6 mA
Function Table
Inputs
Data I/O
*
Function
G
DIR
CPAB
CPBA
SAB
SBA
A
0
–A
7
B
0
–B
7
H
H
H
X
X
X
H or L
L
X
H or L
X
L
X
X
X
X
X
X
Isolation
Clock A
n
Data into A Register
Clock B
n
Data into B Register
Input
Input
L
L
L
L
H
H
H
H
X
X
X
X
X
L
L
H
H
X
X
X
X
A
n
to B
n
DReal Time (Transparent Mode)
Clock A
n
Data into A Register
A Register to B
n
(Stored Mode)
Clock A
n
Data into A Register and Output to B
n
L
H or L
L
Input
Output
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
L
L
H
H
B
n
to A
n
DReal Time (Transparent Mode)
Clock B
n
Data into B Register
B Register to A
n
(Stored Mode)
Clock B
n
Data into B Register and Output to A
n
L
H or L
L
Output
Input
*
The data output functions may be enabled or disabled by various signals at the G and DIR Inputs. Data input functions are always enabled; i.e., data at the bus
pins will be stored on every LOW-to-HIGH transition of the clock inputs.
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Irrelevant
L
e
LOW-to-HIGH Transition
3
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