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參數(shù)資料
| 型號(hào)： | 74F598 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 8-bit shift register with input storage registers(3-State)(帶輸入存儲(chǔ)寄存的8位移位寄存器（三態(tài)）) |
| 中文描述： | 8位輸入存儲(chǔ)寄存器（3態(tài)）（帶輸入存儲(chǔ)寄存的移位寄存器的8位移位寄存器（三態(tài)）） |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 115K |
| 代理商： | 74F598 |
Philips Semiconductors
Product specification
74F598
8-bit shift register with input storage registers (3-State)
2
1991 Oct 21
853–1583 04407
FEATURES
High impedance PNP base input for reduced loading (20
μ
A in
High and Low states)
8–bit parallel storage register
Shift register has asynchronous direct overriding reset
Shift load SHLD is functional when SHCP is Low and locked out
when SHCP is High.
Guaranteed shift frequency DC to 105MHz
Parallel 3–State I/O storage register inputs and shift register
parallel outputs
DESCRIPTION
The 74F598 consists of an 8–bit storage register feeding a
parallel–in/serial–in, parallel–out/serial–out 8–bit shift register. Both
the storage register and shift register have positive edge–triggered
clocks. The shift register has asynchronous reset and when SHCP
is Low, it has asynchronous load.
The shift register load function has been modified to load when both
SHLD and SHCP are Low. When SHCP is High the shift register
load operation is not performed. Data will be properly shifted on the
rising edge of SHCP when SHLD is High.
TYPE
TYPICAL SHCP f
max
TYPICAL SUPPLY
CURRENT (TOTAL)
74F598
100MHz
75mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±
10%,
T
amb
= 0
°
C to +70
°
C
N74F598N
PKG DWG #
20–pin plastic DIP
SOT146-1
20–pin plastic SOL
N74F598D
SOT163-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.) High/
Low
LOAD VALUE
High/Low
I/On
Parallel data input
1.0/0.033
20
μ
A/20
μ
A
20
μ
A/20
μ
A
20
μ
A/20
μ
A
20
μ
A/20
μ
A
20
μ
A/20
μ
A
20
μ
A/20
μ
A
20
μ
A/20
μ
A
20
μ
A/20
μ
A
20
μ
A/20
μ
A
Ds0, Ds1
Serial data inputs
1.0/0.033
SHCP
Shift register clock pulse input
1.0/0.033
STCP
Storage register clock pulse input
1.0/0.033
SHCPEN
Shift register clock pulse enable input
1.0/0.033
SHLD
Shift register load input (active Low)
1.0/0.033
SHRST
Shift register reset input (active Low)
1.0/0.033
S
Serial data select input
1.0/0.033
OE
Output enable input
1.0/0.033
Qs
Serial data output
50/33
1.0mA/20mA
I/On
Parallel data outputs
150/40
3.0mA/24mA
Note to input and output loading and fan out table
1. One (1.0) FAST unit load is defined as: 20
μ
A in the High state and 0.6mA in the Low state.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20 V
CC
S
DS0
DS1
OE
STCP
SHCPEN
SHCP
SHRST
Qs
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
SHLD
GND
SF00375
LOGIC SYMBOL
Qs
V
= Pin 20
GND = Pin 10
S
OE
STCP
SHCPEN
SHCP
SHRST
SHLD
19
16
15
14
13
12
9
11
Ds0
18
Ds1
17
I/O0
1
I/O1
2
I/O2
3
I/O3
4
I/O4
5
I/O5
6
I/O6
7
I/O7
8
SF00376
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74F604 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual octal latch 3-State |
| 74F620 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Inverting Octal Bus Transceiver with 3-STATE Outputs |
| 74F620 WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| 74F620N | 制造商:NXP Semiconductors 功能描述: |
| 74F620PC | 功能描述:總線收發(fā)器 Inv Oct Bus Trans RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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