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參數(shù)資料
| 型號(hào)： | 74F574SJX |
| 元件分類： | 通用總線功能 |
| 英文描述： | Octal D-Type Flip-Flop |
| 中文描述： | 八路D類觸發(fā)器 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 81K |
| 代理商： | 74F574SJX |
www.fairchildsemi.com
2
7
Unit Loading/Fan Out
Function Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW to HIGH Clock Transition
Not LL = CS and PE should never both be LOW voltage level at the same time.
Pin Names
Description
U.L.
Input I
IH
/I
IL
Output I
OH
/I
OL
70
μ
A/
0.2 mA
3 mA/24 mA
5
μ
A/
0.2 mA
5
μ
A/
0.2 mA
5
μ
A/
0.2 mA
5
μ
A/
0.2 mA
5
μ
A/
0.2 mA
5
μ
A/
0.2 mA
5
μ
A/
0.2 mA
5
μ
A/
0.2 mA
5
μ
A/
0.2 mA
1 mA/5 mA
HIGH/LOW
3.5/0.333
75/15
0.25/0.333
0.25/0.333
0.25/0.333
0.25/0.333
0.25/0.333
0.25/0.333
0.25/0.333
0.25/0.333
0.25/0.333
25/12.5
I/O
0
–
I/O
7
Data Inputs or
3-STATE Outputs
Parallel Enable Input (Active LOW)
Up-Down Count Control Input
Master Reset Input (Active LOW)
Synchronous Reset Input (Active LOW)
Count Enable Parallel Input (Active LOW)
Count Enable Trickle Input (Active LOW)
Chip Select Input Active (Active LOW)
Output Enable Input (Active LOW)
Clock Pulse Input (Active Rising Edge)
Terminal Count Output (Active LOW)
PE
U/D
MR
SR
CEP
CET
CS
OE
CP
TC
MR
SR
CS
PE
CEP CET U/D
OE
CP
Function
X
X
X
L
H
H
H
H
H
H
X
X
X
X
L
H
H
H
H
H
H
L
L
X
X
L
(Not LL)
(Not LL)
(Not LL)
(Not LL)
X
H
H
X
X
L
X
X
X
X
X
X
H
X
L
L
X
X
X
X
X
X
X
H
L
L
X
X
X
X
X
X
X
X
H
L
X
H
L
X
X
X
X
X
X
X
X
X
X
X
I/O
a
to I/O
h
in High Z (PE Disabled)
I/O
a
to I/O
h
in High Z
Flip-Flop Outputs Appear on I/O Lines
Asynchronous Reset for all Flip-Flops
Synchronous Reset for all Flip-Flops
Parallel Load all Flip-Flops
Hold
Hold (TC Held HIGH)
Count Up
Count Down
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