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參數(shù)資料
| 型號(hào)： | 74F2953 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Registered transceiver, non-inverting 3-State |
| 中文描述： | 注冊(cè)收發(fā)器，非反相三態(tài) |
| 文件頁數(shù)： | 7/14頁 |
| 文件大?。?/td> | 142K |
| 代理商： | 74F2953 |
Philips Semiconductors
Product specification
74F2952, 74F2953
Transceivers
1989 Sep 22
7
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST CONDITIONS
1
LIMITS
UNIT
MIN
TYP
2
MAX
A0 A7
A0–A7
= 3mA
I
OH
= –3mA
±
10% V
CC
±
5% V
CC
±
10% V
CC
±
5% V
CC
±
10% V
CC
±
5% V
CC
±
10% V
CC
±
5% V
CC
2.4
V
V
OH
High level output voltage
High-level output voltage
V
CC
= MIN,
V
IL
= MAX,
V
IH
= MIN
2.7
3.3
V
B0 B7
B0–B7
= 15mA
I
OH
= –15mA
2.0
V
2.0
V
A0 A7
A0–A7
I
OL
= 24mA
0.35
0.50
V
V
OL
Low level output voltage
Low-level output voltage
V
CC
= MIN,
V
IL
= MAX,
V
IH
= MIN
0.35
0.50
V
B0 B7
B0–B7
I
OL
= 48mA
I
OL
= 64mA
0.38
0.55
V
0.42
0.55
V
V
IK
Input clamp voltage
V
CC
= MIN, I
I
= I
IK
–0.73
–1.2
V
I
Input current at maximum
input voltage
in ut voltage
CPAB, CPBA,
OEAB, OEBA,
CEAB, CEBA
V
CC
= 5.5V, V
I
= 7.0V
100
μ
A
I
A0–A7,
B0–B7
V
CC
= 5.5V, V
I
= 5.5V
1
mA
I
IH
High-level input current
CPAB, CPBA,
OEAB, OEBA,
CEAB, CEBA
V
CC
= MAX, V
I
= 2.7V
20
μ
A
I
IL
Low-level input current
CPAB, CPBA,
OEAB, OEBA,
CEAB, CEBA
V
CC
= MAX, V
I
= 0.5V
–0.6
mA
I
IH
+I
OZH
Off-state output current
High-level voltage applied
A0–A7,
B0–B7
V
CC
= MAX, V
O
= 2.7V
70
μ
A
I
IL
+I
OZL
Off-state output current
Low-level voltage applied
A0–A7,
B0–B7
V
CC
= MAX, V
O
= 0.5V
–600
μ
A
I
OS
Short circuit output current
Short-circuit output current
3
A0–A7
= MAX V
V
CC
= MAX, V
O
= 0V
–60
–150
mA
B0–B7
–100
–225
mA
I
CCH
i
CCL
I
CCZ
90
140
mA
I
CC
Supply current (total)
V
CC
= MAX
120
175
mA
105
155
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25
°
C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
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