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參數(shù)資料
| 型號： | 74F259 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Latch |
| 中文描述： | 鎖存 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 95K |
| 代理商： | 74F259 |
Philips Semiconductors
Product specification
74F259
Latch
1989 Apr 11
3
LOGIC SYMBOL
V
= Pin 16
GND = Pin 8
E
MR
14
15
SF00824
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
4
5
6
7
9
10
11
12
13
3
D
A3
1
A0
2
A1
IEC/IEEE SYMBOL
G8
14
13
15
Z10
SF00825
Z9
1
2
3
9, 10D
10m 0R
9, 10D
10m 1R
9, 10D
10m 2R
9, 10D
10m 3R
9, 10D
10m 4R
9, 10D
10m 5R
9, 10D
10m 6R
9, 10D
10m 7R
0
0
7
2
4
5
6
7
9
10
11
12
8M
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING MODE
MR
E
D
A0
A1
A2
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
L
H
X
X
X
L
L
L
L
L
L
L
L
L
Master Reset
L
L
d
L
L
L
Q=d
L
L
L
L
L
L
L
L
L
d
H
L
L
L
Q=d
L
L
L
L
L
L
L
L
d
L
H
L
L
L
Q=d
L
L
L
L
L
Demultiplex
(active-High decoder
D H)
when D=H)
L
L
d
H
H
H
L
L
L
L
L
L
L
Q=d
H
H
X
X
X
X
q0
q1
q2
q3
q4
q5
q6
q7
Store (do nothing)
H
L
d
L
L
L
Q=d
q1
q2
q3
q4
q5
q6
q7
H
L
d
H
L
L
q0
Q=d
q2
q3
q4
q5
q6
q7
H
L
d
L
H
L
q0
q1
Q=d
q3
q4
q5
q6
q7
Addressable Latch
H
L
d
H
H
H
q0
q1
q2
q3
q4
q5
q6
Q=d
H =
L
X =
d
q
High voltage level
Low voltage level
Don’t care
High or Low data one setup time prior to the Low-to-High Enable transition
Lower case letters indicate the state of the referenced output established during the last cycle in which it was addressed or cleared.
=
=
=
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| 74F260 | Dual 5-input NOR gate |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74F259PC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Addressable D-Type Latch |
| 74F259QC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Addressable D-Type Latch |
| 74F259SC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Addressable D-Type Latch |
| 74F260 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual 5-input NOR gate |
| 74F260D | 制造商:North American Philips Discrete Products Div 功能描述:Logic Circuit, Dual 5-Input NOR, F-TTL, 14 Pin, Plastic, SOP 制造商:NXP Semiconductors 功能描述:Logic Circuit, Dual 5-Input NOR, F-TTL, 14 Pin, Plastic, SOP |
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