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參數(shù)資料
| 型號： | 74F195A |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 4-bit parallel-access shift register(4位并行訪問移位寄存器) |
| 中文描述： | 4位并行存取移位寄存器（4位并行訪問移位寄存器） |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 74K |
| 代理商： | 74F195A |
Philips Semiconductors
Product specification
74F195A
4-bit parallel-access shift register
1996 Mar 12
5
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
NO TAG
MIN
TYP
NO TAG
MAX
UNIT
V
OH
High level output voltage
High-level output voltage
V
= MIN, V
= MAX
CC
V
IH
= MIN, I
OH
= MAX
±
10%V
CC
±
5%V
CC
±
10%V
CC
±
5%V
CC
2.5
V
IL
2.7
3.4
V
V
OL
Low level output voltage
Low-level output voltage
V
= MIN, V
= MAX
CC
V
IH
= MIN, I
OL
= MAX
0.35
0.50
V
IL
0.35
0.50
V
IK
I
I
I
IH
I
IL
I
OS
I
CC
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25
°
C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
Input clamp voltage
V
CC
= MIN, I
I
= I
IK
V
CC
= MAX, V
I
= 7.0V
V
CC
= MAX, V
I
= 2.7V
V
CC
= MAX, V
I
= 0.5V
V
CC
= MAX
V
CC
= MAX
–0.73
–1.2
V
Input current at maximum input voltage
74F195A
100
μ
A
μ
A
High-level input current
all others
20
Low-level input current
Short-circuit output current
3
74F195A
–600
mA
–60
–150
mA
Supply current (total)
74F195A
40
58
mA
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
V
CC
= +5V
T
amb
= +25
°
C
C
L
= 50pF, R
L
= 500
V
CC
= +5V
±
10%
T
amb
= 0
°
C to +70
°
C
C
L
= 50pF, R
L
= 500
UNIT
MIN
TYP
MAX
MIN
MAX
f
MAX
Maximum clock
frequency
Load mode
Waveform
NO TAG
165
180
150
MHz
Shift mode
180
190
170
t
PLH
t
PHL
t
PLH
t
PHL
Propagation delay
CP to Qn
Waveform
NO TAG
3.0
2.5
5.0
4.0
9.5
7.0
2.5
2.0
10.0
7.5
ns
Propagation delay
CP to Q3
Waveform
NO TAG
2.0
2.0
5.5
4.0
9.5
6.5
2.5
2.0
9.5
7.0
ns
t
PHL
Propagation delay
MR to Qn
Waveform 2
2.0
4.0
7.0
2.0
7.0
ns
t
PLH
Propagation delay
MR to Q3
Waveform 2
2.5
4.5
8.0
2.0
10.0
ns
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