參數(shù)資料
型號(hào): 74F194
廠商: NXP Semiconductors N.V.
英文描述: 4-bit bidirectional universal shift register(4位雙向通用移位寄存器)
中文描述: 4位雙向通用移位寄存器(4位雙向通用移位寄存器)
文件頁數(shù): 5/10頁
文件大小: 89K
代理商: 74F194
Philips Semiconductors
Product specification
74F194
4-bit bidirectional universal shift register
April 4, 1989
5
DC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
TEST CONDITIONS
1
LIMITS
UNIT
MIN
TYP
2
MAX
V
OH
High level output voltage
High-level output voltage
3
V
CC
= MIN, V
IL
= MAX
V
IH
= MIN, I
OH
= MAX
V
CC
= MIN, V
IL
= MAX
V
IH
= MIN, I
OL
= MAX
V
CC
= MIN, I
I
= I
IK
V
CC
= MAX, V
I
= 7.0V
V
CC
= MAX, V
I
= 2.7V
V
CC
= MAX, V
I
= 0.5V
V
CC
= MAX
V
CC
= MAX
±
10%V
CC
±
5%V
CC
±
10%V
CC
±
5%V
CC
2.5
V
2.7
3.4
V
OL
Low level output voltage
Low-level output voltage
0.30
0.50
V
0.30
0.50
V
IK
I
I
I
IH
I
IL
I
OS
I
CC
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
= 5V, T
= 25
°
C.
3. Output High state will change to Low stat if an external voltage of less than 0.0V is applied.
4. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
5. With all outputs open, D
i
inputs grounded and a 4.5V applied to S0, S1, MR and the serial inputs, I
CC
is tested with a momentary ground,
then 4.5V applied to CP.
Input clamp voltage
–0.73
–1.2
V
Input current at maximum input voltage
100
μ
A
μ
A
High-level input current
20
Low-level input current
Short-circuit output current
4
Supply current (total)
5
–0.6
mA
–60
–150
mA
33
46
mA
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
V
CC
= +5.0V
T
= +25
°
C
C
L
= 50pF, R
L
= 500
V
CC
= +5.0V
±
10%
T
amb
= 0
°
C to +70
°
C
C
L
L
= 500
UNIT
MIN
TYP
MAX
MIN
MAX
f
MAX
t
PLH
t
PHL
Maximum clock frequency
Waveform 1
105
150
90
MHz
Propagation delay
CP to Qn
Waveform 1
3.5
3.5
5.2
5.5
7.0
7.0
3.5
3.5
8.0
8.0
ns
t
PHL
Propagation delay
MR to Qn
Waveform 2
4.5
8.6
12.0
4.5
14.0
ns
AC SETUP REQUIREMENTS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
V
CC
= +5.0V
T
= +25
°
C
C
L
= 50pF, R
L
= 500
V
CC
= +5.0V
±
10%
T
amb
= 0
°
C to +70
°
C
C
L
L
= 500
UNIT
MIN
TYP
MAX
MIN
MAX
t
S
(H)
t
S
(L)
t
h
(H)
t
h
(L)
t
S
(H)
t
S
(L)
t
h
(H)
t
h
(L)
t
W
(H)
t
W
(L)
t
REC
Setup time, High or Low
Dn, D
SL
, D
SR
to CP
Hold time, High or Low
Dn, D
SL
, D
SR
to CP
Setup time, High or Low
Sn to CP
Waveform 3
4.0
4.0
4.0
4.0
ns
Waveform 3
0
0
1.0
1.0
ns
Waveform 3
8.0
8.0
9.0
8.0
ns
Hold time, High or Low
Sn to CP
Waveform 3
0
0
0
0
ns
CP Pulse width, High
Waveform 1
5.0
5.5
ns
MR Pulse width, Low
Waveform 2
5.0
5.0
ns
Recovery time, MR to CP
Waveform 2
7.0
8.0
ns
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