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參數(shù)資料
| 型號： | 74F191 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通用總線功能 |
| 英文描述： | Up/down binary counter with reset and ripple clock |
| 中文描述： | 上/下的復位和時鐘波紋二進制計數(shù)器 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 104K |
| 代理商： | 74F191 |
Philips Semiconductors
Product specification
74F191
Up/Down binary counter with reset and ripple clock
2
1995 Jul 17
853–0352 15459
FEATURES
High speed –125MHz typical f
MAX
Synchronous, reversible counting
4-Bit binary
Asynchronous parallel load capability
Cascadable without external logic
Single up/down control input
DESCRIPTION
The 74F191 is a 4-bit binary counter. It contains four edge-triggered
master/slave flip-flops with internal gating and steering logic to
provide asynchronous preset and synchronous count-up and
count-down operations.
Asynchronous parallel load capability permits the counter to be
preset to any desired number. Information present on the parallel
data inputs (D
0
- D
3
) is loaded into the counter and appears on the
outputs when the Parallel Load (PL) input is Low. This operation
overrides the counting function. Counting is inhibited by a High level
on the count enable (CE) input. When CE is Low, internal state
changes are initiated. Overflow/underflow indications are provided
by two types of outputs, the Terminal Count (TC) and Ripple Clock
(RC).
The TC output is normally Low and goes High when: 1) the count
reaches zero in the countdown mode or 2) reaches “15” in the count
up mode. The TC output will remain High until a state change
occurs, either by counting or presetting, or until U/D is changed. TC
output should not be used as a clock signal because it is subject to
decoding spikes. The TC signal is used internally to enable the RC
output. When TC is High and CE is Low, the RC follows the clock
pulse. The RC output essentially duplicates the Low clock pulse
width, although delayed in time by two gate delays.
PIN CONFIGURATION
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
CE
Q
0
D
0
D
1
Q
1
D
2
Q
2
GND
CP
Q
3
D
3
V
CC
U/D
RC
TC
PL
SF00729
TYPE
TYPICAL f
MAX
TYPICAL
SUPPLY CURRENT
(TOTAL)
74F191
125MHz
40mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±
10%,
T
amb
= 0
°
C to +70
°
C
N74F191N
PKG DWG #
16-pin plastic DIP
SOT38-4
16-pin plastic SO
N74F191D
SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F(U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
D
0
- D
3
Data inputs
1.0/1.0
20
μ
A/0.6mA
CE
Count enable input (active Low)
1.0/3.0
20
μ
A/1.8mA
CP
Clock pulse input (active rising edge)
1.0/1.0
20
μ
A/0.6mA
PL
Asynchronous parallel load control input (active Low)
1.0/1.0
20
μ
A/0.6mA
U/D
Up/down count control input
1.0/1.0
20
μ
A/0.6mA
Q
0
- Q
3
Flip-flop outputs
50/33
1.0mA/20mA
RC
Ripple clock output (active low)
50/33
1.0mA/20mA
TC
Terminal count output
50/33
1.0mA/20mA
NOTE:
One (1.0) FAST Unit Load (U.L.) is defined as: 20
μ
A in the High state and 0.6mA in the Low state.
相關PDF資料 |
PDF描述 |
|---|---|
| 74F191 | Up/Down Binary Counter with Preset and Ripple Clock |
| 74F191SC | Up/Down Binary Counter with Preset and Ripple Clock |
| 74F191SJ | Up/Down Binary Counter with Preset and Ripple Clock |
| 74F191PC | Up/Down Binary Counter with Preset and Ripple Clock |
| 74F191 | Up/Down Binary Counter with Preset and Ripple Clock |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 74F191_07 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Up/Down Binary Counter with Preset and Ripple Clock |
| 74F191DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Synchronous Up/Down Counter |
| 74F191DCQB | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Up/Down Binary Counter with Preset and Ripple Clock |
| 74F191DCX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Up/Down Binary Counter with Preset and Ripple Clock |
| 74F191DMQB | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Up/Down Binary Counter with Preset and Ripple Clock |
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