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參數(shù)資料
| 型號： | 74F173 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Quad D-type flip-flop 3-State |
| 中文描述： | 四D型觸發(fā)器三態(tài) |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 88K |
| 代理商： | 74F173 |
Philips Semiconductors
Product specification
74F173
Quad D-type flip–flop (3-State)
August 31, 1990
5
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
MIN
NOM
MAX
V
CC
V
IH
V
IL
I
Ik
I
OH
I
OL
Supply voltage
4.5
5.0
5.5
V
High–level input voltage
2.0
V
Low–level input voltage
0.8
V
Input clamp current
–18
mA
High–level output current
–15
mA
Low–level output current
48
mA
°
C
T
amb
Operating free air temperature range
0
+70
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST
LIMITS
TYP
2
UNIT
CONDITIONS
1
MIN
MAX
V
CC
= MIN, V
IL
= MAX,
±
10%V
CC
2.4
V
V
OH
High-level output voltage
V
IH
= MIN, I
OH
= MAX
±
5%V
CC
2.7
3.4
V
V
CC
= MIN, V
IL
= MAX,
±
10%V
CC
2.0
V
V
IH
= MIN, I
OH
= –15mA
±
5%V
CC
2.0
3.1
V
V
OL
Low-level output voltage
V
CC
= MIN, V
IL
= MAX,
V
IH
= MIN, I
OL
= MAX
V
CC
= MIN, I
I
= I
IK
V
CC
= MAX, V
I
= 7.0V
V
CC
= MAX, V
I
= 2.7V
V
CC
= MAX, V
I
= 0.5V
±
10%V
CC
±
5%V
CC
0.35
0.50
V
0.35
0.50
V
V
IK
I
I
I
IH
I
IL
Input clamp voltage
–0.73
-1.2
V
μ
A
μ
A
Input current at maximum input voltage
100
High–level input current
20
Low–level input current
–0.6
mA
I
OZH
Off–state output current, high–level voltage applied
V
CC
= MAX, V
O
= 2.7V
50
μ
A
I
OZL
Off–state output current, low–level voltage applied
V
CC
= MAX, V
O
= 0.5V
–50
μ
A
I
OS
Short–circuit output current3
V
CC
= MAX
-60
-150
mA
I
CCH
I
CCL
I
CCZ
19
26
mA
I
CC
Supply current (total)
V
CC
= MAX
27
37
mA
23
32
mA
Notes to DC electrical characteristics
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25
°
C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
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