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參數(shù)資料
| 型號： | 74F169 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通用總線功能 |
| 英文描述： | 4-bit up/down binary synchronous counter |
| 中文描述： | 4位向上/向下二進制同步計數(shù)器 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 116K |
| 代理商： | 74F169 |
Philips Semiconductors
Product specification
74F169
4-bit up/down binary synchronous counter
1996 Jan 05
3
LOGIC SYMBOL
9
3
4
5
6
15
11
12
13
14
1
2
7
10
CP
CEP
CET
PE
D
0
D
1
D
2
D
3
Q
0
Q
1
Q
2
Q
3
TC
U/D
SF00786
V
= Pin 16
GND = Pin 8
LOGIC SYMBOL (IEEE/IEC)
M4 [DOWN]
9
1
10
7
2
[1]
3
4
5
6
1, 7D
14
13
12
11
M1 [LOAD]
SF00787
M2 [COUNT]
M3 [UP]
CTR DIV 16
[2]
[4]
[8]
15
3, 5 CT=15
4, 5 CT=0
G5
G6
2, 3, 5, 6+/C7
2, 4, 5, 6–
FUNCTIONAL DESCRIPTION
The 74F169 uses edge-triggered J-K-type flip-flops and have no
constraints on changing the control or data input signals in either
state of the clock. The only requirement is that the various inputs
attain the desired state at least a setup time before the rising edge
of the clock and remain valid for the recommended hold time
thereafter. The parallel load operation takes precedence over the
other operations, as indicated in the Mode Select Table. When PE is
Low, the data on the D
0
- D
3
inputs enter the flip-flops on the next
rising edge of the Clock. In order for counting to occur, both CEP
and CET must be Low and PE must be High; the U/D input
determines the direction of counting. The Terminal Count (TC)
output is normally High and goes Low, provided that CET is Low,
when a counter reaches zero in the Count Down mode or reaches
15 in the Count Up mode. The TC output state is not a function of
the Count Enable Parallel (CEP) input level. Since the TC signal is
derived by decoding the flip-flop states, there exists the possibility of
decoding spikes on TC. For this reason the use of TC as a clock
signal is not recommended (see logic equations below).
1) Count Enable = CEP
CET
PE
2) Up: TC = Q
0
Q
3
(U/D)
CET
3) Down: TC = Q
0
Q
1
Q
2
Q
3
(U/D)
CET
MODE SELECT — FUNCTION TABLE
INPUTS
OUTPUTS
Q
n
L
H
OPERATING MODE
CP
U/D
CEP
CET
PE
D
n
l
X
TC
↑
↑
X
X
X
X
X
X
l
(1)
(1)
Parallel load (Dn
→
Qn)
X
↑
h
l
l
h
X
Count Up
(1)
Count Up (increment)
↑
l
l
l
h
X
Count Down
(1)
Count Down (decrement)
↑
↑
X
X
h
X
X
X
h
h
X
X
q
n
q
n
(1)
H
Hold (do nothing)
H = High voltage level steady state
h = High voltage level one setup time prior to the Low-to-High clock transition
L = Low voltage level steady state
l
= Low voltage level one setup time prior to the Low-to-High clock transition
q = Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition
X = Don’t care
↑
= Low-to-High clock transition
(1)= The TC is Low when CET is Low and the counter is at Terminal Count.
Terminal Count Up is (HHHH) and Terminal Count Down is (LLLL).
相關PDF資料 |
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| 74F169 | 4-Stage Synchronous Bidirectional Counter |
| 74F169PC | 4-Stage Synchronous Bidirectional Counter |
| 74F169SC | 4-Stage Synchronous Bidirectional Counter |
| 74F169SJ | 4-Stage Synchronous Bidirectional Counter |
| 74F169 | 4-Stage Synchronous Bidirectional Counter |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 74F169_WFH3026B WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| 74F169DC | 制造商:Texas Instruments 功能描述: |
| 74F169PC | 功能描述:計數(shù)器 IC 4-State Sy Bidir Ctr RoHS:否 制造商:NXP Semiconductors 計數(shù)器類型:Binary Counters 邏輯系列:74LV 位數(shù):10 計數(shù)法: 計數(shù)順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel |
| 74F169PC_Q | 功能描述:計數(shù)器 IC 4-State Sy Bidir Ctr RoHS:否 制造商:NXP Semiconductors 計數(shù)器類型:Binary Counters 邏輯系列:74LV 位數(shù):10 計數(shù)法: 計數(shù)順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel |
| 74F169SC | 功能描述:計數(shù)器移位寄存器 4-State Sy Bidir Ctr RoHS:否 制造商:Texas Instruments 計數(shù)器類型: 計數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
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