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參數(shù)資料
| 型號(hào)： | 74F161APCQR |
| 元件分類(lèi)： | 通用總線(xiàn)功能 |
| 英文描述： | Synchronous Up Counter |
| 中文描述： | 同步設(shè)立攤位 |
| 文件頁(yè)數(shù)： | 3/8頁(yè) |
| 文件大小： | 94K |
| 代理商： | 74F161APCQR |
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Functional Description
The 74F161A and 74F163A count in modulo-16 binary
sequence. From state 15 (HHHH) they increment to state 0
(LLLL). The clock inputs of all flip-flops are driven in paral-
lel through a clock buffer. Thus all changes of the Q outputs
(except due to Master Reset of the 74F161A) occur as a
result of, and synchronous with, the LOW-to-HIGH transi-
tion of the CP input signal. The circuits have four funda-
mental modes of operation, in order of precedence:
asynchronous
reset (74F161A), synchronous
(74F163A), parallel load, count-up and hold. Five control
inputs
—
Master Reset (MR, 74F161A), Synchronous Reset
(SR, 74F163A), Parallel Enable (PE), Count Enable Paral-
lel (CEP) and Count Enable Trickle (CET)
—
determine the
mode of operation, as shown in the Mode Select Table. A
LOW signal on MR overrides all other inputs and asynchro-
nously forces all outputs LOW. A LOW signal on SR over-
rides counting and parallel loading and allows all outputs to
go LOW on the next rising edge of CP. A LOW signal on PE
overrides counting and allows information on the Parallel
Data (P
n
) inputs to be loaded into the flip-flops on the next
reset
rising edge of CP. With PE and MR ('F161A) or SR
(74F163A) HIGH, CEP and CET permit counting when
both are HIGH. Conversely, a LOW signal on either CEP or
CET inhibits counting.
The 74F161A and 74F163A use D-type edge triggered flip-
flops and changing the SR, PE, CEP and CET inputs when
the CP is in either state does not cause errors, provided
that the recommended setup and hold times, with respect
to the rising edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is
HIGH and the counter is in state 15. To implement synchro-
nous multi-stage counters, the TC outputs can be used
with the CEP and CET inputs in two different ways. Please
refer to the 74F568 data sheet. The TC output is subject to
decoding spikes due to internal race conditions and is
therefore not recommended for use as a clock or asynchro-
nous reset for flip-flops, counters or registers.
Logic Equations: Count Enable
=
CEP
CET
PE
TC
=
Q
0
Q
1
Q
2
Q
3
CET
Mode Select Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Note 1:
For 74F163A only
State Diagram
Block Diagram
SR
(Note 1)
PE
CET
CE
P
Action on the Rising
Clock Edge (
Reset (Clear)
Load (P
n
→
Q
n
)
Count (Increment)
No Change (Hold)
No Change (Hold)
)
L
H
H
H
H
X
L
H
H
H
X
X
H
L
X
X
X
H
X
L
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74F161APCX | 制造商:FAIRCHILD 制造商全稱(chēng):Fairchild Semiconductor 功能描述:Synchronous Presettable Binary Counter |
| 74F161ASC | 功能描述:計(jì)數(shù)器移位寄存器 Syn 4-Bit Binary Ctr RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類(lèi)型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類(lèi)型: 輸入線(xiàn)路數(shù)量:1 輸出類(lèi)型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| 74F161ASC_Q | 功能描述:計(jì)數(shù)器 IC Syn 4-Bit Binary Ctr RoHS:否 制造商:NXP Semiconductors 計(jì)數(shù)器類(lèi)型:Binary Counters 邏輯系列:74LV 位數(shù):10 計(jì)數(shù)法: 計(jì)數(shù)順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel |
| 74F161ASCQR | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Synchronous Up Counter |
| 74F161ASCX | 功能描述:計(jì)數(shù)器移位寄存器 Syn 4-Bit Binary Ctr RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類(lèi)型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類(lèi)型: 輸入線(xiàn)路數(shù)量:1 輸出類(lèi)型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
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