參數(shù)資料
型號(hào): 74AVCM162836
廠商: NXP Semiconductors N.V.
英文描述: 20-bit registered driver with inverted register enable and 15 ohm termination resistors 3-State
中文描述: 帶反相寄存使能和15歐終端電阻器的20位三態(tài)寄存驅(qū)動(dòng)器
文件頁(yè)數(shù): 2/10頁(yè)
文件大?。?/td> 99K
代理商: 74AVCM162836
Philips Semiconductors
Product specification
74AVCM162836
20-bit registered driver with inverted register enable
and 15
termination resistors (3-State)
2
2001 Apr 20
853-2175 26096
FEATURES
Wide supply voltage range of 1.2 V to 3.6 V
Complies with JEDEC standard no. 8-1A/5/7.
CMOS low power consumption
Input/output tolerant up to 3.6 V
Low inductance multiple V
CC
and GND pins for minimum noise
and ground bounce
Integrated 15
termination resistors to minimize output overshoot
and undershoot
Full PC133 solution provided when used with PCK2510S and
CBT16292
DESCRIPTION
The 74AVCM162836 is a 20-bit universal bus driver. Data flow is
controlled by output enable (OE), latch enable (LE) and clock inputs
(CP).
This product is designed to have an extremely fast propagation
delay and a minimum amount of power consumption.
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pullup resistor (Live
Insertion).
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
OE
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
GND
V
CC
GND
Y
7
Y
8
Y
9
Y
10
Y
11
Y
12
GND
Y
13
Y
14
Y
15
V
CC
Y
16
Y
17
GND
Y
18
Y
19
NC
CP
A
0
A
1
GND
A
2
A
3
V
CC
A
4
A
5
A
6
GND
A
7
A
8
A
9
A
10
A
11
A
12
GND
A
13
A
14
A
15
V
CC
A
16
A
17
GND
A
18
A
19
LE
SH00159
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
2.0 ns; C
L
= 30 pF.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
An to Yn
V
CC
= 1.8 V
V
CC
= 2.5 V
V
CC
= 3.3 V
V
CC
= 1.8 V
V
CC
= 2.5 V
V
CC
= 3.3 V
2.6
2.0
1.7
ns
t
PHL
/t
PLH
Propagation delay
LE to Yn;
CP to Yn
3.0
2.4
2.0
ns
C
I
Input capacitance
5.0
pF
C
PD
Power dissipation capacitance per buffer
V = GND to V
CC1
Outputs enabled
25
pF
Output disabled
6
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ (C
L
×
V
CC2
×
f
o
) where: f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V; (C
L
×
V
CC2
×
f
o
) = sum of outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE
RANGE
–40
°
C to +85
°
C
ORDER CODE
DRAWING
NUMBER
SOT364-1
56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II
74AVCM162836DGG
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74AVCM62836 20-bit registered driver with inverted register enable with 15Ω termination resistors (3-State)(帶15Ω終端電阻的具有反相寄存使能的20位寄存驅(qū)動(dòng)器(三態(tài)))
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