參數(shù)資料
型號: 74AVC16835A
廠商: NXP Semiconductors N.V.
英文描述: 18-bit registered driver with Dynamic Controlled Outputs (3-State)(具有動態(tài)控制輸出的18位寄存驅(qū)動器(三態(tài)))
中文描述: 18位注冊的驅(qū)動程序與動態(tài)(3態(tài))(具有動態(tài)控制輸出的18位寄存驅(qū)動器(三態(tài))控制輸出)
文件頁數(shù): 7/10頁
文件大?。?/td> 92K
代理商: 74AVC16835A
Philips Semiconductors
Preliminary specification
74AVC16835A
18-bit registered driver with
Dynamic Controlled Outputs
(3-State)
2000 May 02
7
AC WAVEFORMS FOR V
CC
= 3.0 V TO 3.6 V
RANGE
V
M
= 0.5 V
V
X
= V
OL
+ 0.300 V
V
Y
= V
OH
– 0.300 V
V
OL
and V
OH
are the typical output voltage drop that occur with the
output load.
V
I
= V
CC
AC WAVEFORMS FOR V
CC
= 2.3 V TO 2.7 V AND
V
CC
< 2.3 V RANGE
V
M
= 0.5 V
CC
V
X
= V
OL
+ 0.15 V
V
Y
= V
– 0.15 V
V
and V
OH
are the typical output voltage drop that occur with the
output load.
V
I
= V
CC
A
INPUT
t
PHL
t
PLH
V
OL
V
I
GND
V
OH
Y
OUTPUT
SH00132
V
M
V
M
NOTE: V
M
= 0.5V
CC
at V
CC
= 2.3 to 2.7 V
Waveform 1. Input (An) to output (Yn) propagation delay
LE INPUT
Yn OUTPUT
V
I
GND
V
OH
V
OL
t
PHL
t
PLH
t
W
SH00134
V
M
V
M
V
M
NOTE: V
M
= 0.5V
CC
at V
CC
= 2.3 to 2.7V
Waveform 2. Latch enable input (LE) pulse width, the latch
enable input to output (Yn) propagation delays.
CP INPUT
Yn OUTPUT
V
I
GND
V
OH
V
OL
t
PHL
t
PLH
t
W
1/f
MAX
SH00135
V
M
V
M
V
M
NOTE: V
M
= 0.5V
CC
at V
CC
= 2.3 to 2.7 V
Waveform 3. The clock (CP) to Yn propagation delays, the
clock pulse width and the maximum clock frequency.
ééé
ééé
ééééééééé
ééééééééé
ééééééééé
An
INPUT
LE
INPUT
t
SU
NOTE:
The shaded areas indicate when the input is permitted to change
for predictable output performance.
V
M
= 0.5V
CC
at V
CC
= 2.3 to 2.7V
t
SU
V
GND
V
I
GND
SH00133
V
M
V
M
Waveform 4. Data set-up and hold times for the An input to the
LE input
V
I
GND
éééé
éééé
éééé
ééééééé
ééééééé
ééééééé
An INPUT
V
I
GND
V
OH
Yn OUTPUT
V
OL
CP INPUT
t
su
t
su
NOTE:
The shaded areas indicate when the input is permitted to change
for predictable output performance.
V
M
= 0.5V
CC
at V
CC
= 2.3 to 2.7 V
SH00136
V
M
V
M
Waveform 5. Data set-up and hold times for the An input to the
clock CP input
t
PLZ
t
PZL
V
I
nOE INPUT
GND
V
CC
OUTPUT
LOW-to-OFF
OFF-to-LOW
V
OL
V
OH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
GND
outputs
enabled
outputs
enabled
outputs
disabled
t
PHZ
V
M
V
M
V
M
t
PZH
V
X
V
Y
SH00137
NOTE: V
M
= 0.5V
CC
at V
CC
= 2.3 to 2.7 V
Waveform 6. 3-State enable and disable times
相關(guān)PDF資料
PDF描述
74AVC16835 18-bit registered driver 3-State
74AVC16835DGG 18-bit registered driver 3-State
74AVC16836A 20-bit registered driver with inverted register enable and Dynamic Controlled OutputsE (3-State)(具有動態(tài)控制輸出和反相寄存使能的20位寄存驅(qū)動器(三態(tài)))
74AVC16836 20-bit registered driver with inverted register enable 3-State
74AVC16836DGG 20-bit registered driver with inverted register enable 3-State
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