參數(shù)資料
型號: 74AVC16834A
廠商: NXP Semiconductors N.V.
英文描述: 18-bit registered driver with inverted register enable and Dynamic Controlled Outputs (3-State)
中文描述: 帶反相控制使能和動態(tài)控制輸出(3態(tài))的18位驅(qū)動器
文件頁數(shù): 2/13頁
文件大?。?/td> 121K
代理商: 74AVC16834A
Philips Semiconductors
Product data
74AVC16834A
18-bit registered driver with inverted register enable
and Dynamic Controlled Outputs
(3-State)
2
2002 Sep 11
FEATURES
Wide supply voltage range of 1.2 V to 3.6 V
Complies with JEDEC standard no. 8-1A/5/7
CMOS low power consumption
Input/output tolerant up to 3.6 V
DCO (Dynamic Controlled Output) circuit dynamically changes
output impedance, resulting in noise reduction without speed
degradation
Low inductance multiple V
CC
and GND pins for minimum noise
and ground bounce
Power off disables 74AVC16834A outputs, permitting Live
Insertion
Integrated input diodes to minimize input overshoot and
undershoot
Full PC133 solution provided when used with PCK2509S or
PCK2510S and CBT16292
DESCRIPTION
The 74AVC16834A is a 18-bit universal bus driver. Data flow is
controlled by output enable (OE), latch enable (LE) and clock inputs
(CP).
This product is designed to have an extremely fast propagation
delay and a minimum amount of power consumption.
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pullup resistor (Live
Insertion).
A Dynamic Controlled Output (DCO) circuitry is implemented to
support termination line drive during transient. See the graphs on
page 9 for typical curves.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
NC
NC
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
GND
V
CC
GND
Y
6
Y
7
Y
8
Y
9
Y
10
Y
11
GND
Y
12
Y
13
Y
14
V
CC
Y
15
Y
16
GND
Y
17
OE
LE
GND
NC
A
0
GND
A
1
A
2
V
CC
A
3
A
4
A
5
GND
A
6
A
7
A
8
A
9
A
10
A
11
GND
A
12
A
13
A
14
V
CC
A
15
A
16
GND
A
17
CP
GND
SH00156
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
2.0 ns; C
L
= 30 pF.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
An to Yn
V
CC
= 1.8 V
V
CC
= 2.5 V
V
CC
= 3.3 V
V
CC
= 1.8 V
V
CC
= 2.5 V
V
CC
= 3.3 V
2.6
2.0
1.7
ns
t
PHL
/t
PLH
Propagation delay
LE to Yn;
CP to Yn
2.9
2.3
1.9
ns
C
I
Input capacitance
5.0
pF
C
PD
Power dissipation capacitance per buffer
V = GND to V
CC1
Outputs enabled
25
pF
Output disabled
6
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
×
V
CC2
×
f
+ (C
×
V
CC2
×
f
) where: f
= input frequency in MHz; C
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V; (C
L
×
V
CC2
×
f
o
) = sum of outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE
RANGE
–40
°
C to +85
°
C
–40
°
C to +85
°
C
ORDER CODE
DRAWING
NUMBER
SOT364-1
56-Pin Plastic 0.5 mm pitch TSSOP
74AVC16834ADGG
56-Pin Plastic 0.4 pitch TSSOP (TVSOP)
74AVC16834ADGV
SOT481-2
相關(guān)PDF資料
PDF描述
74AVC16834 18-bit registered driver with inverted register enable 3-State
74AVC16834DGG 18-bit registered driver with inverted register enable 3-State
74AVC16835A 18-bit registered driver with Dynamic Controlled Outputs (3-State)(具有動態(tài)控制輸出的18位寄存驅(qū)動器(三態(tài)))
74AVC16835 18-bit registered driver 3-State
74AVC16835DGG 18-bit registered driver 3-State
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74AVC16834ADGG,118 功能描述:總線收發(fā)器 18-BIT REG DRV/INV RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
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