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參數(shù)資料
| 型號： | 74AUP1G32 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Low-power 2-input OR gate |
| 中文描述： | 低功耗2輸入或門 |
| 文件頁數(shù)： | 1/20頁 |
| 文件大小： | 97K |
| 代理商： | 74AUP1G32 |
1.
General description
The 74AUP1G79 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specied for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backow current through
the device when it is powered down.
The 74AUP1G79 provides the single positive-edge triggered D-type ip-op. Information
on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock
pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock
transition for predictable operation.
2.
Features
s Wide supply voltage range from 0.8 V to 3.6 V
s High noise immunity
s Complies with JEDEC standards:
x JESD8-12 (0.8 V to 1.3 V)
x JESD8-11 (0.9 V to 1.65 V)
x JESD8-7 (1.2 V to 1.95 V)
x JESD8-5 (1.8 V to 2.7 V)
x JESD8-B (2.7 V to 3.6 V)
s ESD protection:
x HBM JESD22-A114-C exceeds 2000 V
x MM JESD22-A115-A exceeds 200 V
x CDM JESD22-C101-C exceeds 1000 V
s Low static power consumption; ICC = 0.9 A (maximum)
s Latch-up performance exceeds 100 mA per JESD 78 Class II
s Inputs accept voltages up to 3.6 V
s Low noise overshoot and undershoot < 10 % of VCC
s IOFF circuitry provides partial Power-down mode operation
s Multiple package options
s Specied from
40 °Cto+85 °C and 40 °C to +125 °C
74AUP1G79
Low-power D-type ip-op; positive-edge trigger
Rev. 01 — 12 September 2005
Product data sheet
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74AUP1G3208 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Low-power 3-input OR-AND gate |
| 74AUP1G3208GF | 制造商:NXP Semiconductors 功能描述:IC 3 INPUT OR-AND GATE XSON6 |
| 74AUP1G3208GF,132 | 功能描述:邏輯門 1.8V 1G LO-PWR RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| 74AUP1G3208GF-H | 功能描述:邏輯門 1.8V 1G LO-PWR 3-INPT OR-AND RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| 74AUP1G3208GM | 制造商:NXP Semiconductors 功能描述:IC 3 INPUT OR-AND GATE XSON6 |
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